Abstract: One of the main difficulties in post-silicon validation is the limited debug access bandwidth to internal signals. At the same time, SoC devices often contain dedicated bus-based test access mechanisms (TAMs) that are used to transfer test data between external testers and embedded cores. In this paper, we propose to reuse these precious TAM resources for real-time debug data transfer in post-silicon validation. This strategy significantly increases debug bandwidth with negligible routing overhead. To support different TAM architectures and debug scenarios, design for debug (DfD) structures are introduced at both core test wrapper level and system level. Simulation results demonstrate the effectiveness of the proposed approach at low DfD cost.

Abstract: The present invention is generally directed towards providing a method, system and article of manufacture for generating and utilizing debug history to improve the debugging process. By providing facilities to store and retrieve debug history records for given events, the present invention allows developers to debug code more efficiently by allowing them to leverage information stored in a debug history repository. Further, the added functionality, related to the debug history, is available via modules that work in conjunction with existing debugger applications and is provided to users via a variety of interfaces including graphic interfaces and plug-in components.

Abstract: A debugging method and apparatus for developing telecom-class service based on model driven. It is achieved to combine the debugging information of the code debugger and the model display to complete the graphics context debugging of the telecom-class service based on model driven through inversely searching the diagram element according to the code when the graphics context debugging is being carried. The debugging method and apparatus provide debugging ability based on MDA for the telecom-class service development tool, realize to arrive at the actual graphics context debugging not using any simulator, and realize the graphics context debugging of the telecom-class service based on model driven of the remote files.

Abstract: We present a methodology to debug a SOC by concentrating on its communication. Our extended communication model includes a) multiple signal groups per interface protocol at each IP port, b) the handshakes per signal group (e.g. for command), and c) the handshakes within a signal group (e.g. for write and read data elements). As a result, our debug methodology is the first to offer debug control at three communication granularities: individual data elements in a message, messages (i.e. requests or responses), and entire transactions. Communication to distributed shared memories is supported in networks on chip (NOC) by transparently (demultiplexing different master-slave channels based on the memory address, also called narrowcast. In this paper, we extend previous work on NOC debug that allowed per-connection debug (i.e. a master without differentiating between its slaves) to also support per-channel (i.e. per master-slave pair) debugging, also for narrowcast connections. This enables essential fine-grained debug control for multi-processor SOCs that use distributed-shared-memory communication. The debug infrastructure consists of hardware components, and a software API and library. We define the hardware infrastructure and the required changes to a NOC. Our architecture cleanly separates the monitoring and distribution of events from how they are interpreted and used, in terms of hardware and programming. We define a high-level software API for run-time user control. The debug methodology offers run-time programmable breakpoints, stopping, continuing, and single-stepping of distributed- shared memory communication at three granularities, at the cost of 2.5% NOC area increase and no speed penalty.

Abstract: A debugging device configured to debug a program includes an analysis section configured to analyze information of a code that does not need to be debugged in which a predetermined processing instruction is described, the code being generated by optimization of a compiler for a source code of the program, and an output section configured to output processing content information, a start address, and an end address of the code that does not need to be debugged which are obtained by the analysis.

Abstract: Cross-trigger, the mechanism to trigger activities in one debug entity from debug events happened in another debug entity, is a very useful technique for debugging applications involving multiple embedded cores. Existing solutions rely on dedicated interconnects (i.e., different from functional interconnects) to transfer debug events and cannot guarantee the arrival time of the debug events coincides with the arrival time of the data messages between multiple cores. This results in mismatches between the observed system internal operations and the ones that designers expect to watch. To tackle the above problem, in this paper, we propose to package the cross-trigger events and the actual data together into transaction messages and transfer them along the same functional interconnects (namely in- band debug event transmission), with the help of novel design-for- debug circuits. Simulation results on a hypothetical NoC-based systems show the effectiveness of the proposed technique.

Abstract: Existing SoC debug techniques mainly target bus-based systems. They are not readily applicable to the emerging system that use Network-on-Chip (NoC) as on-chip communication scheme. In this paper, we present the detailed design of a novel debug probe (DP) inserted between the core under debug (CUD) and the NoC. With embedded configurable triggers, delay control and timestamping mechanism, the proposed DP is very effective for inter-core transaction analysis as well as controlling embedded cores' debug processes. Experimental results show the functionalities of the proposed DP and its area overhead1.

Abstract: An in-process debugging experience can be implemented using an infrastructure that supports out-of-process debugging. A program that is to be debugged may be written in a command-line language that receives and processes input through an input loop. The interpreter for the language runs in a first process. A helper program is started in a second process, and attaches to the first process as if it were an out-of-process debugger. A debugging module is loaded into the interpreter, which provides user debugging commands that may utilize the helper program. When the program to be debugged generates a debug event, the event is received by the helper process, which uses a debug primitive to start a new instance of the input loop in the first process. Debugging commands provided by the debugging module can be entered by the user into the new instance of the input loop.

Abstract: A messaging system based group joint debugging system is provided, comprising a master computer and a slave computer in mutual communication with the master computer through network. With the group joint debugging system, multiple members of a geographical distributed development team can do jobs on a same debugging session. The master computer includes capabilities for obtaining a debugging request message containing a debugging command via the messaging system, extracting the debugging command and calling a corresponding debugging function of the program debugger according to the debugging command, and sending execution result of the called debugging function, as a debugging response message, to computers participating in a group joint debugging, such that the group joint debugging is carried out to the program to be debugged. The slave computer includes capabilities for receiving the debugging response message and carrying out automatic debugging on the program according to the debugging command.

Abstract: This paper presents design-for-debug (DfD) methods for the reuse of network-on-chip (NoC) as a debug data path in an NoC-based system-on-chip (SoC). We propose on-chip core debug supporting logics which can support transaction-based debug. A debug interface unit is also presented to enable debug data transfer through an NoC between an external debugger and a core-under-debug (CUD). The proposed approach supports debug of designs with multiple clock domains. It also supports collection of trace signatures to facilitate debug of long pattern sequences. Experimental results show that single and multiple stepping through transactions are feasible with moderately low area overhead. We also present simulation result to verify proper operation of the debug components.

Abstract: A semiconductor IC capable of debugging two or more processors at the same time by means of a single debugger and a semiconductor IC test system. The semiconductor IC includes processors operating at different frequencies, a trigger circuit which causes all of the processors to be in a debugging state when one of the processors is in the debugging state, and a JTAG circuit applying a boundary scan operation to the processors connected to a JTAG pin in series.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to source code debugging and provide a method, system and computer program product for debug tours for debugging source code In an embodiment of the invention, a debugger data processing system can be provided The system can include a debugger executing in a host computing platform, and a debug tour manager coupled to the debugger The debug tour manager can include program code enabled to load a debug tour of an ordered set of breakpoints established during a prior debugging session of source code, to apply the breakpoints in the debug tour to separately loaded source code, and to execute the source code and to invoke the applied breakpoints in an order prescribed by the ordered set within the debugger

Abstract: A system and process for debugging of a computer program, is provided. One implementation includes a function configured for including mark-up information marking certain methods as special fields in a source code of the application program, such annotations denoting debugging instructions and indications of which methods are intended for debugging only; a processing module configured for generating a production version of the application program including the same semantics as the original application program but potentially fewer methods and no debug related annotations, wherein methods that are not annotated as debugging only methods are maintained; and a debugger configured for debugging purposes using the debugging methods.

Abstract: An on-chip debug emulator is capable of connecting to the target device and the host device for remotely debugging the program in the target device. The on-chip debug emulator contains a debug communication control unit. This debug communication control unit contains a plurality of serial communication circuits, the plurality of serial communication circuits are commonly provided with a clock signal. The debug communication control unit controls communications with the target device based on commands output from the host device. Each of The plurality of serial communication circuits contains a data buffer and serially transmits data stored in the data buffer to and from the target device while synchronized with the clock signal. Namely, the plurality of serial communication circuits communicate in parallel while operating synchronized with the same clock. The on-chip debug emulator can in this way be made utilizing a low-cost microcomputer not containing any parallel communication circuits.

Abstract: An in-circuit debugging (ICD) system includes at least a first target processor, an embedded debug mode with a debug information memory (DIM), a debug host, and an ICD bridge. The first target processor has an embedded debug module (EDM) and performs a program code in normal mode, where the first EDM controls the first target processor in debug mode. The DIM stores debug information for debugging in debug mode, and is invisible to the first target processor when the first target processor operates in normal mode. The debug host has debug software, and is utilized for debugging the program code by using the debug information in debug mode. The ICD bridge has a host debug module (HDM) coupled to the first EDM, and is coupled between the first target processor and the debug host and utilized for bridging information communicated between the first target processor and the debug host.

Abstract: A method and a system for providing customizable, process-specific Just-In-Time debugging in operating system is provide in this invention The method comprises the following steps: obtaining process-specific JIT debugging information, in response to the occurrence of an trap event in operating system; invoking the debugger corresponding to the process according to the obtained process-specific JIT debugging information This method and system supports per-process JIT debugging configuration

Abstract: In this paper, we describe the implementation of memory checking functionality based on instrumentation using Valgrind-Memcheck tool. The combination of Valgrind based checking functions within the MPI-implementation offers superior debugging functionalities, for errors that otherwise are not possible to detect with comparable MPI-debugging tools. The functionality is integrated into Open MPI as the so-called memchecker-framework. This allows other memory debuggers that offer a similar API to be integrated. The tight control of the user’s memory passed to Open MPI, allows not only to find application errors, but also helps track bugs within Open MPI itself. We describe the actual checks, classes of errors being found, how memory buffers internally are being handled, show errors actually found in user’s code and the performance implications of this instrumentation.

Abstract: A processor, a multiprocessor, and a debugging method for solving the conventional problems, one of which is very difficult to switch among debug programs and start the selected program within a certain time. The above convention problem can be solved by a processor that includes a debug unit block, a multimode debug interrupt control block, and an execution block. The debug unit block monitors the execution of the debug target user program and issues a debug interrupt when a predetermined debug condition is satisfied. The control block, upon receiving such a debug interrupt, specifies a debug mode that selects a predetermined debug program. When the debug unit block issues such a debug interrupt, the execution block selects and executes a debug program according to the debug mode specified by the control block.

Abstract: A process and system for debugging of a computer program, is provided. One implementation involves including mark-up information into source code of the application program, generating a debug-enabled version of the computer program including debugging methods based on the mark-up information, and providing the debug-enabled version of the program computer to a debugger for debugging purposes using the debugging methods.

Abstract: The invention is a method and apparatus for debugging of software on an array-type single chip computer system 16 without provision of dedicated debugging hardware on the chip. This is accomplished by suitable operating instructions that cause a hardware portion of array 16 to operate as a virtual background debug mode port 10 for one 12 and more hardware portions in the array. Virtual debug port 10 communicates with an adjacent target hardware portion 12 via their common directly connected single-drop bus 16, and with an external user interface system through an input/output (I/O) port 28, by passing the debugging information through other hardware portions 52 of the array to a peripheral hardware portion 22 adapted with the I/O port 28. The method of the present invention includes a retriever program, sometimes called a “head segment”, operating in the virtual debug port hardware portion, and further software portions referred to as “stream segment” and “tail segment” which are resident and operating in other hardware portions of the array and which interoperate cooperatively with the retriever program to implement communication of data and instructions between the virtual debug port and the user interface. The method includes a portion referred to as “delivery segment” which is prepared by the user and transmitted from the user interface system to the chip, and contains the head segment, stream segments, and tail segment programs as a payload, which it delivers and stores in appropriate other hardware portions of array 16.

Abstract: A method, system and apparatus of a secure debug interface and memory of a media security circuit and method are disclosed. In one embodiment, a host processor, an external hardware circuit to encrypt an incoming data bit communicated to a debug interface using a debug master key stored at a pointer location of a memory (e.g., the memory may be any one of a flash memory and/or an Electrically Erasable Programmable Read-Only Memory (EEPROM)) and to decrypt an outgoing data bit from the debug interface using the debug master key, and a media security circuit having the debug interface to provide the pointer location of the memory having the debug master key to the external hardware circuit.

Abstract: A method uses an integrated circuit having a debug status register. The integrated circuit is for being debugged by a hardware debugger external to the integrated circuit and has a processing unit for executing debug software. The debug status register is coupled to the processing unit and is for being coupled to the hardware debugger. The method includes updating the debug status register with hardware status flags arising from running the hardware debugger and software status flags arising from running the debug software. The method further includes masking locations in the debug status register where the hardware status flags are located from being read by the debug software while allowing the hardware status flags and the software status flags to be read by the hardware debugger. This is particularly useful in using the hardware debugger in debugging the debug software.

Abstract: A debug device of embedded systems is provided. The embedded system includes an embedded processor for reading a bootloader from a flash memory through a data flash interface. The debug device includes a memory transmission interface, a dada storage module, a data control module and a display module. The memory transmission interface is configured to couple the data flash interface for receiving data to the data storage module. The data control module determines whether the data stored in the data storage module is data from a data bus or from the data flash interface according to whether a data control signal of the data flash interface has been triggered. The display module displays the data of the data storage module.

Abstract: This paper provides and overview of the {\it GDBase} framework for offline parallel debuggers. The framework was designed to become the basis of debugging tools which scale successfully on systems with tens to hundreds of thousands of cores. With several systems coming online at more than 50,000 cores in the past year, debuggers which can run at these scales are now required. The proposed framework offers two features not found in current generation debugging tools: the ability to debug "offline'', and a central database to act as a repository of debugging information. These two features enable the GDBase debugger to offer several advantages. The debugger can be used in conjunction with modern batch systems with low overhead, with user interaction taking place after the parallel system resources are freed. The use of a database and a simple API allows for multiple interfaces and data mining tools to be implemented to provide novel ways of viewing and analyzing debugging data. The database also enables cross-run analysis, and the combination of debugging, performance, and system health information. Evidence is provided of the scalability of the framework, as well as output from several simple analysis tools that have been implemented.

Abstract: The in-circuit emulator (ICE) is commonly adopted as a microprocessor debugging technique. In this paper, a parameterized embedded in-circuit emulator and its retargetable debugging software are proposed. The parameterized embedded in-circuit emulator can be integrated into different style processors such as microcontroller, microprocessor, and DSP processor. The GUI interface debugging software can help user to debug easily. As a result of it, the duration of microprocessor debugging design procedure time is reduced.

Abstract: A gdb-based debugging system for OpenRISC1200 Processor based on IEEE1149.1 JTAG interface is developed. Unlike usual gdb-based embedded debugging systems, this system uses the hardware debugging modules in OpenRISC1200 Processor to extend GDB. Its debugging agent doesnpsilat work on the target but on the host computer, so it can work well without any target operating system support. In this paper, the systempsilas general frame design and realization of the main modules are explained in detail. It is verified by both FPGA prototype emulation and software simulation. It establishes a good foundation for further development on OpenRISC.

Abstract: A method includes providing an integrated circuit having a plurality of debug resources. The debug resources are usable exclusively for debug operations. The debug operations include operations directed by debug software executed by the integrated circuit and operations directed by external debug hardware which is external to the integrated circuit. The method further includes enabling availability of a first portion of the debug resources for use by the debug software, where a second portion of the debug resources are committed for exclusive use by the external debug hardware. The first portion is exclusive of the second portion. The method includes performing operations directed by the debug software using at least one debug resource of the first portion of the debug resources and operations directed by the external debug hardware using at least one debug resource of the second portion of the debug resources.

Abstract: Since its introduction, test access port has become an inseparable part of the majority of integrated circuits. Commonly referred to as JTAG, it meant to provide a solution to the problem of testing assembled printed circuit boards as well as a means of accessing and controlling on-chip test-dedicated features. With appearance and ever increasing complexity of multi-processor system-on-chip integrated circuits, the architectural variety and intended roles of JTAG based test features significantly expanded. Observability and controllability of an integrated circuitpsilas functionality for debug and test, security protection, power management, clocking schemes management is only a partial list of the features a JTAG based test and debug controller supports in a modern system-on-chip. This paper presents a categorization and analysis of debug port controller architectures and their key features for use in system-on-chip integrated circuits.

Abstract: A system comprises debug logic usable to debug the system. The system also comprises processing logic capable of accessing the debug module using electronic signals. The system further comprises security logic configured to prevent the processing logic from accessing the debug logic unless the security logic is provided with a passkey that matches another passkey stored in the system.