Abstract: A method and apparatus for debugging of OS kernel and applications software that does not require use of a hardware probe; can debug both user-mode programs and a significant body of the OS kernel code; allows the OS to continue servicing exceptions while debugging; leverages OS built-in device drivers for communicating devices to communicate with the host debugger; and can debug a production version of the OS kernel. When debugging is required, the running OS kernel dynamically loads a software-based debug agent on demand whereby such debug agent dynamically modifies the running production OS kernel code and data to intercept debugging traps and provide run-control. To provide debugging of loadable module, the debug agent implement techniques to intercept the OS module loading system call; set breakpoints in the loaded module initialization function; calculate the start address of the debugged module in memory; and asynchronously put the system under debug. By structuring command loop to execute in non-exception mode, and devising a process to transfer execution from the debug agent exception handler to the debug agent command loop and back, the debug agent can communicate with the host debugger using interrupt-driven input/output devices as well as allowing the system to service interrupts while under debug.

Abstract: Efficient test and debug techniques are indispensable for performance characterization of large complex integrated circuits in deep-submicron and nanometer technologies. Performance characterization of such chips requires on-chip hardware and efficient debug schemes in order to reduce time to market and ensure shipping of chips with lower defect levels. In this paper we present an on-chip scheme for delay fault detection and performance characterization. The proposed technique allows for accurate measurement of delays of speed paths for speed binning and facilitates a systematic and efficient test and debug scheme for delay faults. The area overhead associated with the proposed technique is very low.

Abstract: In this paper, we give an overview of the silicon debug process. We discuss the procedure of debug, along with the current state of the art tools and design features used to assist in the process of doing debug. In conclusion, we discuss what new challenges lay ahead in the area of silicon debug.

Abstract: This paper describes a novel technique to reuse the existing scanpaths in a chip for delay fault testing and silicon debug. Efficient test and debug techniques for VLSI chips are indispensable in Deep Submicron technologies. A systematic debug scheme is also necessary in order to reduce time-to-market. Due to stringent timing requirements of modern chips, test and debug schemes have to be tailored for detection and debug of functional defects as well as delay faults quickly and efficiently. The proposed technique facilitates an efficient scheme for detecting and debugging delay faults and has minimal area and power overhead.

Abstract: An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

Abstract: A method for debugging a read only memory (ROM) in a wireless target device is disclosed. A wireless communication link is established between the target device and a host computer. A debug mode change command is received from the host computer by the application program running on the target device via a wireless communication interface in the target device. The wireless communication interface is parsed with the monitor program. A debug instruction is received by the monitor program from a debugger in the host computer where the debug instruction includes an entry address and a jump address. The application program jumps to the received jump address upon reaching the entry address location. An acknowledgement is transmitted from the target device to the debugger in the host computer, and, in response to the acknowledgement, a second debug instruction is received from the debugger in the host computer.

Abstract: This paper reports a case study of multiprocessor SoC (MPSoC) design of a complex video encoder, namely OpenDivX. OpenDivX is a popular version of MPEG4. It requires massive computation resources and deals with complex data structures to represent video streams. In this study, the initial specification is given in sequential C code that had to be parallelized to be executed on four different processors. High level programming model, namely Message Passing Interface (MPI) was used to enable inter-task communication among parallelized C code. A four processor hardware prototyping platform was used to debug the parallelized software before final SoC hardware is ready. The targeting of abstract parallel code using MPI to the multiprocessor architecture required the design of an additional hardware-dependent software layer to refine the abstract programming model. The design was made by a team work of three types of designer: application software, hardware-dependent software and hardware platform designers. The collaboration was necessary to master the whole flow from the specification to the platform.The study showed that HW/SW interface debug was the most time-consuming step. This is identified as a potential killer for application-specific MPSoC design. To further investigate the ways to accelerate the HW/SW interface debug, we analyzed bugs found in the case study and the available debug environments. Finally, we address a debug strategy that exploits efficiently existing debug environments to reduce the time for HW/SW interface debug.

Abstract: Summary form only given. This paper describes a parallel debugger and the related debugging support implemented for CHARM++, a data-driven parallel programming language. Because we build extensive debugging support into the parallel runtime system, applications can be debugged at a very high level.

Abstract: The present invention provides an extensible mechanism for displaying object data in a debug environment in a suitable display format. In one aspect, a system is provided for computerized debug environments. The system includes a display component that presents data at a debug interface, wherein the data is associated with a first representation in a debug object and as at least a second representation at the debug interface. A communications component transmits the data from the debug object to the display component and also transforms the data from the first representation to the second representation.

Abstract: This paper describes a debug environment for high performance integrated circuits and systems, running in real-world conditions. With the proposed environment, debug data is collected by a built-in debug hardware module (or integrated probe) and transferred to an external debugger using a dedicated debug port. The external debugger, composed of a FPGA and a processor, uses real-time assertion-based verification techniques to ensure that the system acts according to its specifications. Dynamic changes in the probe configuration allow higher monitoring resolution of critical parts of the circuit or system and improve the use of the debug port bandwidth. This paper discusses advantages and limitations of this technique.

Abstract: Software developers working on multi-language systems can utilize a multi-language debugging environment. The debugging environment can be uniform across languages, and can seamlessly perform debugging between one or more languages in a multi-language environment. Such a system can have a number of attributes intended to help developers facing debugging problems in multi-language environments.

Abstract: Methods, systems, and apparatus are provided for multi-core debugging. A single processor having multiple processing cores dynamically and simultaneously establishes multiple debugging sessions on different ones of the processing cores. Existing applications not associated with the debugging sessions are maintained and processed without interruption and existing states associated with the processor and the processing cores are maintained before and after the debugging sessions are established.

Abstract: Debugging a device, including a device having power-saving features, may include observing and controlling power state transitions.

Abstract: In the case where a break instruction is a predicated instruction whose execution condition is not satisfied in a program debug apparatus, the target program is executed again up to the predicated instruction, that is to be executed next, whose execution condition is satisfied or the non-predicated instruction that is to be executed next.

Abstract: A method for configuring an automated in-circuit test debugger is presented. The novel test debug and optimization configuration technique configures expert knowledge into a knowledge framework for use by an automated test debug and optimization system for automating the formulation of a valid stable in-circuit test for execution on an integrated circuit tester. In a system that includes a rule-based controller for controlling interaction between the test-head controller of an integrated circuit tester and an automated debug system, the invention includes a knowledge framework and a rule-based editor. The knowledge framework stores test knowledge in the representation of rules that represent a debugging strategy. The rule-based editor facilitates the use of rules as knowledge to debug or optimize an in-circuit test that is to be executed on the integrated circuit tester.

Abstract: This work describes a proposal for a model for parallel debugging interfaces. The main goal of this work is to present a parallel debugger interface model that can be used as a base for new interfaces. The advantage of designing interfaces using an existing model is to standardize some features, which could help in transposing one of the main barriers for the effective use of such tools: the need of learning how to use them - which is, in its turn, considered by most of the programmers as "a waste of time". The activities involved in building this model were the identification of useful parallel debugging interface features and the further creation of an ideal set of criteria based on them. This set of criteria was used in building the model as well as in developing an interface prototype for parallel debugging. The prototype is called PADI (Parallel Debugger Interface). It is a front-end to a lower level parallel debugger and implements several features described by the model, developed with the purpose of making parallel debugging an easier task.

Abstract: A system and method to debug a thread without affecting other threads in a virtual machine. A virtual machine (VM) may execute a thread subject to debugging and another thread. An interface to the VM permits only debugging command that are specific to the thread subject to debugging to affect the VM.

Abstract: FPGAs provide powerful hardware emulation platforms for rapid prototyping of digital designs This potential is usually restricted to overall system level emulation, with interactive debugging possibilities limited to the real-time observation of external signals This article describes the most recent advances made in the UNSHADES[1] system, where unlike most commercial packages, signals need not be previously selected, nor are limited in number or size by the internal memory available This system, which adds a small debug controller to the design to be inspected, provides many new design debugging features such as single stepping, state modification or register inspection over the entire design The debug controller provides these powerful debugging operations without the need for large design modification whilst occupying itself very little FPGA resources A minimal debug controller implemented in a virtex-II FPGA requires the occupation of just 3 IO pins and 43 logic slices; over half of these logic slices are dedicated to an optional 32-bit cycle counter

Abstract: FPGAs provide powerful hardware emulation platforms for rapid prototyping of digital designs. This potential is usually restricted to overall system level emulation, with interactive debugging possibilities limited to the real-time observation of external signals. This article describes the most recent advances made in the UNSHADES[1] system, where unlike most commercial packages, signals need not be previously selected, nor are limited in number or size by the internal memory available. This system, which adds a small debug controller to the design to be inspected, provides many new design debugging features such as single stepping, state modification or register inspection over the entire design. The debug controller provides these powerful debugging operations without the need for large design modification whilst occupying itself very little FPGA resources. A minimal debug controller implemented in a virtex-II FPGA requires the occupation of just 3 IO pins and 43 logic slices; over half of these logic slices are dedicated to an optional 32-bit cycle counter.

Abstract: A method and system for monitoring the real-time of software running on a microprocessor system. Debug hardware is used to select a range of instructions or events to be monitored by a performance monitor interval with the microprocessor system. A comparison is made between each event and start and stop events are identified in the debug hardware. The performance monitor is enabled by the debug hardware, when events occur within the range defined by the debug hardware. Use of the debug hardware for enabling performance monitoring avoids any overhead associated with generating interrupts, or additional code in the application program.

Abstract: This paper describes the methods that have been developed for debugging and verifying systems using devices from the picoArray TM family. In order to increase the computational ability of these devices the hardware debugging support has been kept to a minimum and the methods and tools described take this into account. An example of how some of these methods have been used to produce an 802.16 system is given. The important features of the new PC102 device are outlined.

Abstract: SOURCE LEVEL DEBUGGING OF CIRCUITS SYNTHESIZED FROM HIGH LEVEL LANGUAGE DESCRIPTIONS

Abstract: A debugging device and method are provided, including a central processing unit (CPU) connected to a chipset with a system management interrupt pin. The debugging method includes sending out a system management interrupt signal to central processing unit from the system management interrupt pin of the chipset. Then the CPU moves into a system management mode and pops out a debugging operation window for selecting and executing each debugging item. After the execution of each debugging item is completed, the CPU will leave the debugging operation window and return to the next instruction before debugging. After the execution of each debugging item is completed in the debugging operation window, the CPU will return to the operation system and continue the execution of next instruction before debugging. The execution of debugging will not influence the status and the program execution from the operating system. The disclosed debugging method is convenient for executing each debugging item at any time.

Abstract: A method and system to remotely log debug information is described. A computer executing program code generates debug information upon the occurrence of an error in execution. The debug information is then sent to a remote computer using a network adaptor. In one embodiment, the computer executing the program is Extensible Firmware Interface (EFI) compliant.

Abstract: A high speed debug support interface has circuits to interface on-chip debug support circuits to a high bandwidth communications port means located on the surface of a system integrated circuit (101) and to on-chip debug support circuits (100). The communication port means can be realised by bonding or integrating special sender and or receiver cells preferably optical sender cells (103) and or optical receiver cells (110) onto the surface of the system integrated circuit (101). The high speed debug support interface communicates. with on-chip or in-assembly debug support circuits and an external development tool (108) to permit hardware and software related debugging and development activities, including program tracing, data tracing and memory substitution. The high speed debug support interface has circuits to interface on-chip debug support circuits to system resources such as memory located within. the device assembly (102) and connected by the system interconnect.

Abstract: Due to the increasing complexity of electronic systems the controllability and observability of advanced on-chip systems are getting more and more important. The functional density which is measured as the amount of functionality related to port width for outer access is permanently growing. Therefore tasks like manufacturing tests and functional debugging are becoming more difficult. In this work we present a synthesizable model for an integrated test and debugging unit which implements a build-in self test (BIST) and an advanced debugging unit. In the debugging unit the scan-chain from testing is reused to get access to internal registers. The whole unit is designed as a wrapper to system-on-chip (SoC) cores. To assess the usability of this approach the wrapper together with a processor core is prototyped and the functionality of the testing and debugging unit is demonstrated.

Abstract: In this paper, we present a technique and a tool to debug microprocessor systems implemented in FPGAs. We propose a method based on debug logic insertion and a set of debug modules to provide soft core microprocessors with In-Circuit Emulation capabilities.

Abstract: A read only memory circuit for debugging and updating, the circuit includes read only memory, debug program memory, program counter, and compare and load unit. In the circuit, the compare and load unit detects instruction-read-memory-address from the program counter. If the instruction-read-memory-address is a predetermined main program address, the compare and load unit serves to transmit a debug address in the debug program memory to the program counter to update the original instruction-read-memory-address for debugging.