Abstract: A data processing system (10) includes a debug unit (14) that is capable of providing unobtrusive debug capabilities to the normal operation of the data processing system by controlling activation of all or a selected subset of a plurality of subsystems as needed for a debug operation. For example, power can be conserved by activating selected subsystems as needed for a debug operation. Furthermore, in one embodiment, the debug unit provides a level of activation, ranging from deactivation to full activation, to the selected subsystems which provides further control of the data processing system. In one embodiment, debug control and status registers (40) are provided for power management handshaking between the debug unit and the plurality of subsystems. The handshaking can be used to ensure that a debug operation may proceed properly since the selected subsystems are capable of providing status information to the debug unit.

Abstract: Conventional register transfer level (RTL) debugging is based on overlaying simulation results on structural connectivity information of the Hardware Description Language (HDL) source. This process is helpful in locating errors but does little to help designers reason about the how and why. Designers usually have to build a mental image of how data is propagated and used over the simulation run. As designs get more and more complex, there is a need to facilitate this reasoning process, and automate the debugging. In this paper, we present innovative debug techniques to address this shortage in adequate facilities for reasoning about behavior, and debugging errors. Our approach delivers significant technology advances in RTL debugging; it is the first comprehensive and methodical approach of its kind that extracts, analyses, traces, explores, and queries a design's multi-cycle temporal behavior. We show how our automatic tracing scheme can shorten debugging time by orders of magnitude for unfamiliar designs. We also demonstrate how the advanced debug techniques reduce the number of regression iterations.

Abstract: Methods and systems are disclosed for debugging a computer program code by using a debugging software. Software means may be provided for causing the debugging software to stop at a breakpoint set in the computer program code. In one embodiment, a method is provided that comprises making the debugging software stop at a breakpoint based on one or more predefinable conditions.

Abstract: Specific tasks associated with debugging are performed in the background, prior to a user of an application development tool invoking the debugger. The tasks including (1) starting a hosting process, (2) loading a hosted runtime environment (e.g., .NET runtime) in the process, and (3) attaching a debugger to the hosting process, are performed in the background before the user commences debugging. Once the user invokes the debugger, the user's application is executed and debugged. Thus, the perceived time to start debugging is greatly reduced.

Abstract: The present invention provides methods and apparatus, including computer program products, for debugging a computer program running on a system that is separated from the debugging system by at least one firewall. The computer program being debugged can be a Java application. A router on each side of the firewall can be used to establish communication between the two systems. To the debugging system, it appears that the computer program is running locally.

Abstract: The invention relates to debug circuitry (20) and more particularly to a method and apparatus for providing security for debug circuitry (20). In one embodiment, a plurality of non-volatile elements (38) are used in providing selective disabling and re-enabling of at least a portion of the debug circuitry (20). Authentication may also be used. The present invention may use any debug interface, including standard debug interfaces such as the JTAG debug interface defined by the IEEE.

Abstract: This paper presents an on-chip hardware architecture to support application software development for embedded Systems-on-Chips (SoC). This architecture provides debug support for one manufacturer's complete SoC platform. This includes a significant number of 16-bit and 32-bit microcontroller and DSP cores, spanning a multitude of application specific systems ranging from wireless systems to engine controllers. The debug support architecture is modular and can be divided into three main components: i) processor-specific debug resources, ii) a serial communication interface to connect the SoC with a debug host computer system and iii) a number of interconnection links to communicate between the serial communication interface and the processor debug resources. This modular approach allows the debug support architecture to be adapted to almost any system configuration (including multiple processor cores), while keeping the impact on silicon real estate for production devices at a minimum.

Abstract: Trace debugging is a software diagnostic technique for embedded real-time systems. It is developed to give embedded software developers the ability to trace the activity of the processor even when it is operating out of cache. This ability is lost on many high performance processors and in real-time systems. Tools for debugging real-time systems are scarce (Lee, E., 2000; Zhang, L. and Yuan, P., 1999). This paper describes work that was performed on a new method of trace debugging that can be used to aid in real-time debugging of embedded software. The technique described uses non-intrusive measurements that are supplemented with deductive algorithms. The technique developed in the study differs from traditional debuggers by utilizing the a-priori information that is available. The study utilized a Motorola 68020 as a model of a high performance processor, but the processes are applicable to many "high performance" processors.

Abstract: Methods and systems are disclosed for debugging a computer program code by use of a debugging software. Software means may be provided for causing the debugging software to stop at one or more types of breakpoints set in the computer program code. In one embodiment, a debugging method is provided that comprises: debugging a program code with at least one type of breakpoint; and activating or deactivating all breakpoints of the at least one type by a single action.

Abstract: The present invention is a smart card device that can be debugged and software developed using at least one interrupt endpoint without adding an additional port. At least one memory stores a debug monitor program and instructions for completing smart card transactions. An interface is defined by a plurality of communication pipes and respective endpoints, including at least one interrupt endpoint. A microprocessor is operatively connected to the interface and memory and configures the interrupt endpoint as a debug port for debugging and software development using the debug monitor program.

Abstract: Recent technology improvements in the area of embedded processors have changed the methods of debugging and calibration with instruction reconstruction and data collection. This transition has come about in part, due to the System-on-a-Chip (SoC) methodology from silicon vendors and the encapsulation of significant portions of the system on a single piece of silicon. The result is the removal of the external address and data bus and higher performance. Motorola is a leader in the SoC methodology with the integration of Flash memory technology that allows the application to function without an external memory busy The requirements in real time applications such as engine management and transmission systems have brought on a new requirement for the embedded processor vendor to provide real time information. The IEEE-ISTO Nexus 5001 Consortium has been working to provide a real time debug and calibration specification and standard to address these issues.

Abstract: A technique for embedding a microprocessor into an integrated circuit allows on-chip testing and debugging. The microprocessor present on the chip tests and debugs the rest of the chip. Both testing and debugging of a programmable logic device use an embedded microprocessor. Testing is performed by the device manufacturer using a test system. Debugging is performed by a user using a host computer. A PLD includes programmable logic, an embedded microprocessor and separate memory. Testing or debugging routines, patterns, simulations, etc., are downloaded onto the memory. The microprocessor executes the test or debug routine and uploads results to the test system or host computer. The technique is applicable any integrated circuit that can include an embedded microprocessor and associated memory, such as a PLD, an ASIC, a memory chip, or an analog chip.

Abstract: Statistical data show that it is much less expensive to correct software bugs at the early design stage rather than the late stage of the development process when the final system has already been implemented and integrated together. The use of slicing and execution histories as an aid in software debugging is well established for programming languages like C and C++; however, it is rarely applied in the field of software design specification. We propose a solution by applying the source code level technologies to debugging software designs represented in a high-level specification and description language such as SDL. More specifically, we extend execution slice-based heuristics from source code-based debugging to the software design specification level. Suspicious locations in an SDL specification are prioritized by their likelihood of containing faults. Locations with a higher priority should be examined first rather than those with a lower priority as the former are more likely to contain the faults. A debugging tool, SmartD/sub DSL/, with user-friendly interfaces was developed to support our method. An illustration is provided to demonstrate the feasibility of using our method to effectively debug an architectural design.

Abstract: When developing new designs, debugging the prototype is important to resolve application malfunction. During this board design debug, often a few pins of an IC are measured to check signals. Access to these pins is becoming more difficult due to packages like BGA. The JTAG port is an efficient mechanism to gain more access to the ICs. A method is presented to reconfigure the boundary scan chain to any desired length and to access pins involved in the debugging. The method is used asynchronously or synchronously to the test clock. In asynchronous mode high transfer frequencies are possible. For synchronous mode two different variants are described where the data throughput is determined by the intermediate logic. Both modes have proven to work on an FPGA and all implementations fully retain compliancy to the IEEE 1149.1 standard.

Abstract: Java programmers have generally located logical errors with traditional debugging methods until comparatively lately. But, debugging, locating the errors in Java programs, is to be difficult task. And so programmers may spend considerable time debugging the programs. This paper describes the use of simple Hybrid Debugging Technology for locating logical errors in Java programs. This is a debugging technique that combines an algorithmic debugging method with a traditional step-wise debugging method. This approach can improve the drawback of two methods. The importance of this paradigm tries to do towards an automated debugging that users can conveniently debug Java programs.

Abstract: A debugging method is used for the keyboard controller code. Through the breakpoints set at the testing end and loaded debugging program, the keyboard controller code sends state data to the testing end at the breakpoints in accord with the debugging program. The testing end returns commands according to the received state data to trace the execution state of the code, thereby debugging the code procedure.

Abstract: A hardware debug device is usable to debug a target such as a microcontroller or microprocessor. A host instructs the hardware debug device what tests to perform on the target by sending a non-compiled script of text across a standardized script-based interface. The hardware debug device receives and interprets the script and sends appropriate microcommands to the on-chip debugger of the target to carry out actions specified by the script. The syntax of the interpreted script language is rich and allows scripts to define complex looping and testing actions. New scripts can be written to accommodate different target processors without changing the hardware debug device. Because complex testing operations are performed by the hardware debug device, network traffic at the host is reduced. The use of the interpreter and scripts also allows the cost of the hardware debug device to be reduced and reliability of the device to be increased.

Abstract: The invention provides a debug function built-in type microcomputer that is capable of creating a readily analyzable debug environment and compressing output information, even when an output signal line having a bit width fewer than a bit width of a command bus is used to trace contents on the command bus. In a debug function built-in type microcomputer, a DBG (debug unit) outputs information to be traced, and status information indicative of contents of the information to be traced from a status generation circuit.

Abstract: In one embodiment, a system for debugging a software application is provided. A debug agent, being in an executable form, is configured to be combined with an executable form of the software application, and is configured to monitor events from the software application during run-time. A debugger logic is configured to receive data from the debug agent relating to the monitored events and to communicate debugging requests to the debug agent allowing a user to dynamically debug the software application.

Abstract: Methods, systems, and apparatus combine simulation and emulation debugging in a single debugging session. A debugging session is established to debug instructions. During that session a number of the instructions can be processed in a simulation mode or an emulation mode. Processing can be switched between the modes during the session. Coherency is maintained between both modes of operation during the session.

Abstract: This paper describes the architecture of a structural, cost effective debug methodology, applicable to a system on chip in its system environment and targeting software as well as hardware debugging. The highly modular and flexible architecture enables an almost infinite variation of flexible configurable modules designed and hooked up to the test access port (TAP). The hardware configuration flexibility is supported by software running on a PC or workstation, hooked up via a POD connected to the TAP interface. The result is an easy to use implementation of increased observability.

Abstract: A method and apparatus for remotely debugging an application program over the Internet is described. A software vendor provides an interface program along with an application program to a customer. The interface program detects a debug request initiated by a customer operator on a customer computer, and establishes a connection with a debug program on a vendor computer over the Internet. The interface program takes over control of the application program from the customer operator, and takes various actions including running a diagnostic sequence received from the debug program on the application program to debug the application program.

Abstract: A semiconductor integrated circuit device includes: a first semiconductor chip including a CPU and a debug basic circuit section for verifying operation of a program executed by the CPU; and a second semiconductor chip retained over a principal surface of the first semiconductor chip and including a debug extension circuit section electrically connected to the CPU and the debug basic circuit section. The debug basic circuit section includes a debug command analyzing section for analyzing a command input from outside. The debug extension circuit section formed in the second semiconductor chip includes a debugging function circuit section including at least one debug circuit.

Abstract: Embedded programmable systems are becoming common in system designs, resulting in the need for educational institutions to teach advanced embedded systems design and develop debugging competence in students. Remote laboratory experimentation provided as part of a web-based distance learning allows flexible access to on-campus resources free of time or geographical constraints. However, adapting and redeveloping existing software and hardware resources to this purpose is both time consuming and expensive. This paper introduces a remote-access laboratory architecture, which extends current e-learning strategies to provide real-time debugging for embedded programmable systems via the web. An example experiment illustrates the on-chip and off-chip real-time debugging capabilities of the laboratory.

Abstract: Reconfigurable Computers based on a combination of conventional microprocessors and Field Programmable Gate Arrays (FPGAs) presents new challenges to designers. Debugging on such hardware/software cohabiting systems can be a nightmare. This paper presents SONICmole, a debugging environment designed for the UltraSONIC reconfigurable computer, which is designed specifically for real-time video applications. The window-based integrated debugging environment includes a hardware debug module (the "mole") that performs the function of a logic analyzer, embedded within the FPGA design, and an easy-to-use software package that facilitates such a hardware/software system. The resource overhead of the hardware module is only 4% of a Virtex XVC 1000 FPGA. The approach reported here is not limited to the UltraSONIC architecture, and can easily be modified for other reconfigurable computers.

Abstract: : Adaptive computing systems (ACS) are hardware systems based around FPGA technology. Historically, design and debug tools for such systems have been based on ASIC technology. However, FPGA technology provides features which suggest different approaches be used for debug. For example, readback is a feature available in many FPGA devices which provides the ability to query an executing FPGA device for its entire internal state, providing unprecedented visibility into the executing design. The central element of the debug environment developed in this work is a debug services module (DSM). It provides a unified simulation/hardware execution debug environment which allows the user to debug the executing hardware in the context of the original design environment. This means signal values in the executing hardware can be viewed and manipulated using their original signal names from the design source. In addition, the DSM provides the following support for designs running on ACS platforms: checkpointing, multitasking, remote access, and interfacing with external high-level design tools. Finally, the DSM provides support for the automatic synthesis of debug circuitry to enable rapid instrumentation of FPGA designs for debug purposes. This report summarizes the debug system and a number of the experiments completed using it.

Abstract: Using high-level synthesis tools to map programs written in general-purpose languages to FPGA hardware has grown in popularity and it is becoming necessary to provide comprehensive debugging tools in order to verify the correctness of the synthesized hardware Currently, post-synthesis debugging is done at the circuit level This paper discusses the issues, as well as some early results, of creating a source level debugger for hardware synthesized from source code This study is meant to provide some insight into what needs to be added or built into synthesizing compilers in order to allow debug of a synthesized circuit at the source level, which will provide the programmer with a familiar view of the program being debugged

Abstract: A debug device has a serialization section for converting a parallel program to a serial program and creating debug data indicating the corresponding relation between the parallel program and the serial program. The debug device further has a storage section for storing the debug data and a conversion section for mutually converting the corresponding data between the parallel program and the serial program based on the debug data in order for an operator to efficiently perform a debug operation.