Abstract: A coprocessor interface is described which provides a flexible degree of coupling with a host control processor Specific methods are defined for architectures to make use of the interface for supporting client-server coprocessors (CSCOPs) A dynamic debug interface is used to provide a coprocessor interface which supports tightly coupled, loosely coupled and firmly coupled operation

Abstract: A software system and method, using a coordination-centric approach, for debugging distributed software environments is described, wherein the distributed software environment produces event traces to be analyzed by a debugging host. Distributed software environments are connected to debugging hosts either directly or indirectly. In a direct connection, a processing element's runtime system collects event records and sends them to a primary runtime debugging architecture, where the event records are time-stamped and causality-stamped and transferred to an event queue on the debugging host. An indirect connection uses an intermediate runtime debugging architecture, which facilitates the transfer of event records from the processing element to the event queue. Event records also may be collected and stored on a flash memory for post-mortem distributed debugging. Event traces are made visible to the runtime system by inserting event recording calls at significant source lines in the distributed software environment.

Abstract: Since FPGAs are frequently used to improve the time to market for products, shortening the time for validating and debugging FPGA designs is, thus, important. Our paper discusses how directly instrumenting FPGA programming data, or bitstreams, with debugging hardware can improve the debugging productivity for designers and, thus, reduce a design’s time to market. We also provide some background relating to the current state of the art in debugging FPGA designs and describe how bitstream instrumentation can be automated using JHDL, JBits and JRoute. When instrumenting designs with embedded logic analyzers at the bitstream level, we have witnessed design modification speed-ups ranging from about 6 to 19 times over more conventional techniques. We will also briefly mention other applications of bitstream modification in debugging FPGA designs.

Abstract: A debugging subsystem for testing a system-on-a-chip includes an embedded processor and memory and includes at least one debugging subblock monitors a bus between the processor and the memory to detect selected triggering events, counts the number of triggering events detected and when the number of triggering events reaches a predetermined threshold, generates a debugging signal.

Abstract: An active debugging environment for debugging a virtual application that contains program language code from multiple compiled and/or interpreted programming languages The active debugging environment is language neutral and host neutral, where the host is a standard content centric script host with language engines for each of the multiple compiled and/or interpreted programming languages represented in the virtual application The active debugging environment user interface can be of any debug tool interface design The language neutral and host neutral active debugging environment is facilitated by a process debug manager that catalogs and manages application specific components, and a machine debug manager that catalogs and manages the various applications that comprise a virtual application being run by the script host The process debug manager and the machine debug manager act as an interface between the language engine specific programming language details and the debug user interface

Abstract: A semiconductor integrated circuit having: an internal main bus; first microprocessor and second microprocessor sharing the internal main bus; a first debug serial bus with one end thereof connected to said first microprocessor; a second debug serial bus with one end thereof connected to the second microprocessor; and a debugging module connected to the other ends of the first debug serial bus and second debug serial bus and transferring at least a debugging program and debugging data to the first microprocessor via said first debug serial bus and to the second microprocessor via the second debug serial bus.

Abstract: In one embodiment, a debugger for a hardware-implemented operating system that supports one or more processors includes a host debug and a user interface. The host debug is operable to connect to a kernel processing unit of the hardware-implemented operating system via a test interface such as a Joint Test Access Group (JTAG) interface, to request information concerning internal objects of the kernel processing unit during the operation of the processors, and to receive the requested information without disturbing the operation of the processors. The user interface is then used to present the requested information to the user. In one embodiment, the debugger further includes a target resident debug server that is scheduled by the kernel processing unit to execute debugging commands issued by the host debug (e.g., a command to collect information resident in the processor's data space, a command to set a breakpoint, a command to respond to a breakpoint, etc.). The target resident debug server executes the debugging commands without unreasonable interference with the operation of the processors.

Abstract: Software development methods and tools are described to generate visual representations of a system's behavior over time, called “evolution diagrams,” to aid in debugging concurrent software systems. The diagrams take advantage of the exposure provided by coordination interfaces to present more complete views of system executions, explicitly showing events, message traffic between components, etc. The display is presented at a user-selectable hierarchical level of the system design, thus enabling a programmer to work at a design layer where the problem or its effect is easily recognized.

Abstract: A central processing unit (CPU) for easily testing and debugging an application program, which includes a data communications unit for performing data communications with a host computer, a status register having a flag representing whether an operational mode of the CPU is a general operational mode representing a general operational state or a debugging mode representing a debugging state, a debugging stack pointer register which is used as a stack pointer designating a stack memory storing data of a debugging program, and a comparator for comparing a value stored in a break register with break data, wherein the CPU is converted into the debugging mode if the break register value is same as the break data, the flag of the status register has a value representing a debugging mode, a start address for performing a debugging program is loaded in a program counter, and the debugging program is executed to perform a debugging according to a command from the host computer via the data communications unit.

Abstract: Embodiments of the present invention relate to a mechanism to prevent the oscillator from being stopped when a host development system is coupled to the background debug communications interface (52) and the background debug mode has been enabled. This allows background debugging operations to continue when the target data processing system is in a low power mode. Other embodiments relate to a mechanism for allowing a host development system to request a synchronization timing pulse from a target data processing system so the correct clock speed can be determined for background communications. Alternate embodiments relate to a data processing system having a system clock unit and a background debug system (14) where the background debug system includes a background debug clock unit, separate from the system clock unit, and an enable control (44). When the enable control is asserted, the background debug clock unit is enabled, independent of the system clock unit.

Abstract: An embedded system is provided with the capability to be debugged. The embedded system includes a central processing unit (CPU) that is coupled to a bus having certain contents. A register, also with contents, is available for loading by the CPU. Finally, a debug logic circuit is also included. The debug logic circuit is coupled to both the bus and the CPU. The debug circuit itself is composed of a breakpoint detect circuit that is coupled to the bus and to the register. This circuitry enables a breakpoint signal that is produced by the breakpoint detect circuit when the contents of the register equal the contents of the bus. A method is also provided for debugging an embedded system having a microcontroller with a CPU. First, a debug logic circuit that resides on the same chip as the microcontroller is programmed to detect a predetermined condition in the microcontroller. Next, application software is run on the microcontroller. When a predetermined condition is detected, the CPU is interrupted which provides the ability to view the condition of the microcontroller. Programming the debug logic circuit can include the storing of a breakpoint address in a breakpoint address register. Afterward, a program memory address bus is selected for comparison to the contents of the breakpoint address register, upon which time a breakpoint counter is set to zero. The steps of interrupting and detecting are accomplished by comparing the contents of the program memory address bus to the contents of the breakpoint register and, if they are equal, then the CPU is interrupted.

Abstract: Multiple processors of a multiprocessor system are placed into a debug mode of operation approximately simultaneously when one processor initially enters the debug mode as a result of incurring a debug event The other processors enter the debug mode as a result of the one processor asserting a debug event signal upon initially entering the debug mode A logic circuit associated with each processor responds to any debug event signal asserted by another processor and the failure of its associated processor to assert a debug event signal, to assert an external debug break signal to the associated processor and place the associated processor into the debug mode

Abstract: A method, system, and product are disclosed for automatically generating a symbol-based debug script, which is executable by a debug program, for debugging a software program. Function symbols included in the software program are identified. The functions represented by the function symbols may be executed during an execution of the software program. A debug script is then automatically generated which, when executed by a debug program, will record each one of the functions symbols which represent a function called by the software program during execution of the software program by the debug program.

Abstract: Authentication circuits (2-3 to 2-11) are provided between a debug I/F circuit (2-1) and a debug terminal The authentication circuit transmits a transmission key to externally at the time of activation, and authenticates from a received signal and the transmission key, and enables to access a debug I/F It is possible to prevent a spurious access from the debug I/F by a third person by the authentication circuit

Abstract: A computer program debugger is disclosed which stores previous programs which have been debugged and the debug parameters which were considered when debugging. When a new computer program is to be debugged, the new debugger is invoked and it automatically compares the executing program to be debugged with the previous programs. When one or more of the debug parameters are so similar that it can be said that the computer program undergoing debugging matches a previously stored computer program, a user is given options to display the matching programs, the modules, the functions, the lines, and the debug parameters and to exchange debug parameters between the programs which can be used to modify the either or any of the programs. The user is further given the option to store the current program undergoing debugging as a new program to be considered in matching the next program to be debugged. It is further envisioned that the various debug scenarios may be stored and can be recalled separately from the program that generates or uses them.

Abstract: The invention regards a method for interactive debugging and an apparatus for multi-channel, multi-service debugging. The method comprises the steps of: selecting a target construct for debugging, accessing data related to an operation of the target construct by a debug construct, and monitoring at least a portion of the data without disturbing the operation of the target construct to debug the target construct. The apparatus comprises a graphical user interface for providing information about at least one service, an operating system maintaining an isolated debugging environment for each of the at least one service, and a debug core configured to select a target construct for debugging from the at least one service upon a user request.

Abstract: A system and method for debugging a partitioned avionics computer which uses a debugging dump memory and a debugging dump memory controller which take control of the main system bus of the computer for a predetermined amount of time.

Abstract: A debug module ( 20 ) is provided which allows a developer to capture three types of debug information. The three types of debug information are: change-of-flow addresses, CPU data, and current instruction addresses. The debug information is captured in an on-chip debug FIFO memory ( 30 ) during program development. The debug information is provided to an external host via a serial communication interface ( 14 ) for post-processing and analysis. Storing and retrieving program information in this way is useful in microcontrollers that do not provide external access to address and data bus signals.

Abstract: The present invention relates to programming of electronic data carrier applications. In particular, it relates to an improved debugging method and system for chipcard applications. It is based on the principle to use a conventional standard communication protocol between chipcard and terminal application for debugging purposes as well. Primarily, protocol extensions are implemented by special commands according to said protocol, but carrying debug instructions instead of the usual business commands. A wrapper logic wrapping the card driver recognizes due to a control information given in the previous command that the response comprises debug information and sends it to the debug software.

Abstract: A software debugging mechanism for embedded systems is presented. The debugger is a dynamically loadable and linkable module of the operating system. The methodology presented provides automatic error detection, classification and location capabilities for a set of algorithmic errors. An example implementation of our approach is given for debugging an integer divide-by-zero error.

Abstract: Debugging of a transaction across multiple processors is facilitated by having debug information follow the transaction from processor to processor. The transaction can be debugged across processors without predefining the transaction path, and without performing a debug registration process between the client controlling the debugging and each processor of the multiple processors.

Abstract: A debugger program product is described which comprises a computer readable medium having computer program logic stored therein for debugging the operation of a target system which is provided with a microprocessor. The debugger program product including a framework module configured such that it can be dynamically linked to a function module which serves to provide a debug function for use in debugging the operation of the target system and can be connected to a simulator capable of performing the simulation of the target system in order to debug the operation of the target system by the use of the debug function of the function module.

Abstract: In the microcomputer, the debug target circuit and the debugging circuit with an interface module to the in-circuit emulator are independently supplied with drive powers. Drive power is supplied to the debug target circuit and the debugging circuit, and various debug information is set by the in-circuit emulator. Thereafter, only supply of drive power to the debug target circuit is stopped. While the various debug information is held at the debugging circuit, supply of drive power to the debug target circuit is restarted. The debugging just after power throw-in is performed based on the debug information held in the debugging circuit.

Abstract: With the development of VLSI, embedded system is growing sharply. A new methodology, Co-design, appeared to meet needs of embedded system designing. System designers require good EDA tools, which support Co-design methodology. Debug is an important part of design process, so we improved a debug subsystem to fit Co-design. Different from traditional software debug tools, the new debug system was designed to reflect the real and comprehensive status of an embedded system. To achieve this goal, we add a little circuit to original system. The circuit will control the debug process, and collect information that designer focuses. The information covers software and hardware information. All errors, including errors across boundary between software and hardware, will be detected. This debug sub-system have implemented on a co-verification platform. The platform based on a FPGA emulator, so the debug sub-system can be implemented and reconfigured very quickly.

Abstract: The invention relates to a software system and method for dynamically determining debugging information from source code of a program being debugged. In this method, the source code of the program being debugged is presented in an area of a display by the software system. A portion of the source is selected for a debug activity. In response to this selection, a source code object is created that contains debugging information relevant to that portion of source code. Then, a debug activity is initiated by using the debugging information from the source code object. This debug activity may be selected from a menu or be presented in another portion of the display in the form of a parameter input area (dialog). The debugging information in the source code object is used to supply the parameters of the debug activity. If the source code is modified such that the debugging information of a previously selected area is impacted, the associated source code object is updated and any debug activity using that source code object is dynamically updated.

Abstract: This paper presents a novel use of visualization applied to debugging the Cplant/sup TM/ cluster hardware at Sandia National Laboratories. As commodity cluster systems grow in popularity and grow in size, tracking component failures within the hardware will become more and more difficult. We have developed a tool that facilitates visual debugging of errors within the switches and cables connecting the processors. Combining an abstract system model with color-coding for both error and job information enables failing components to be identified.

Abstract: Debugging and testing is a larger part of the effort spent in a software development cycle. Debugging a program is time consuming and is a continuous cycle of code modification and testing. The task of debugging depends on the environment, the language, the operating system; the problem; and more interestingly even the individual program. We present a detailed implementation of software architecture for debugging distributed programs. The debugger based on the proposed architecture supports debugging based on a mechanism for controlling multiple processes, presenting the process states, grouping of processes for ease in controlling the distributed programs developed on PVM based computing paradigm.

Abstract: PROBLEM TO BE SOLVED: To provide a central processing unit to facilitate a test and debugging of a program capable of easily testing and debugging an application program to perform the test and the debugging downloaded from a host computer at a debugging state. SOLUTION: The central processing unit is provided with a data communication part for data communication with the host computer, a state register having a flag to indicate whether an operation mode of the central processing unit is a normal operation mode to indicate a normal operation state or a debugging mode to indicate a debugging state, a debugging stack pointer register to specify a debugging stack area on a memory and a comparing part to make the central processing unit enter the debugging mode when a value stored in a braking register is the same as interruption data, has a value in which the flag indicates the debugging mode by switching the central processing unit to the debugging mode when the value stored in the braking register coincides with the interruption data and the debugging is performed by using the debugging stack pointer register as a stack pointer to specify the memory in which data of the debugging program is stored.