Abstract: A debug port in accordance with the invention provides circuitry for enabling system (hardware and software) development within an inaccessible computer processor. In one embodiment, a debug port is incorporated within the internal logic of a single-chip, reduced instruction set signal processor referred to as the signal processor. A fully implemented debug port is comprised of five interacting functional elements: debug bus unit (DBU), debug command unit (DCU), debug instruction Unit (DIU), debug inject/extract unit (DJU), and a debug flow unit (DFU). The DBU provides circuitry for buffering data received from the signal processor and other functional elements within the debug port as well as accepting data from an external source. The DBU provides for off-chip connections. The DCU provides circuitry for decoding and executing debug commands received by the debug port. The DIU provides circuitry to insert one or more instructions with, or without, data into the instruction stream of the signal processor. The DJU provides circuitry for injecting external sources of information (e.g., an analog input signal, external control signals, or repetitious data signals) into the signal processor under program control. The DFU provides circuitry for monitoring program/task execution.

Abstract: A system for debugging software uses a portable debug environment-independent client debugger object and at least one non-portable server debugger object with platform-specific debugging logic. The client debugger object has a graphic user interface which allows a user to control and manipulate the server debugger object with debug environment-independent debug requests. The server debugger object performs a platform-specific debug operation on the software to be debugged. The platform-specific results generated by the debugging operation are translated to debug environment-independent results and returned to the client debugger object. This operation allows the same client debugger object to be used with one or more server debugger objects running on different platforms.

Abstract: A system provides debugging functions for high-speed processors by adding a comparatively small amount of hardware to the microprocessor. A debugging module which receives part of the debugging function is placed in a microprocessor and is connected with a debugging tool outside the processor. In the debugging module, a processor core in the processor accesses and executes a monitor program in the debugging tool 60 through the debugging module. In the normal mode, while the processor executes a user program, the debugging module receives trace information and sends it to the debugging tool and also performs tasks related to the breakpoints.

Abstract: A system provides debugging functions for high-speed processors by adding a comparatively small amount of hardware to the microprocessor. A debugging module which receives part of the debugging function is placed in a microprocessor and is connected with a debugging tool outside the processor. In the debugging module, a processor core in the processor accesses and executes a monitor program in the debugging tool 60 through the debugging module. In the normal mode, while the processor executes a user program, the debugging module receives trace information and sends it to the debugging tool and also performs tasks related to the breakpoints.

Abstract: One of the interesting problems in hardware-software co-design is that of debugging embedded software in conjunction with hardware. Currently, most software designers wait until a working hardware prototype is available before debugging software. Bugs discovered in hardware during the software debugging phase require re-design and re-fabrication, thereby not only delaying the project but also increasing cost. It also puts software debugging on hold until a new hardware prototype is available. In this paper we describe a hardware-software co-simulator that can be used in the design, debugging and verification of embedded systems. This tool contains simulators for different parts of the system and a backplane which is used to integrate the simulators. This enables us to simulate hardware, software and their interaction efficiently. We also address the problem of simulation speed. Currently, the more accurate (in terms of timing) the models used, the longer it takes to simulate a system. Our main contribution is a set of techniques to speed up simulation of processors and peripherals without significant loss in timing accuracy. Finally, we describe applications used to test the co-simulator and our experience in using it.

Abstract: A debug instruction program is executed to enable a latch contents setting register to select the address of a specified part of a memory to be monitored. The selected address is given to a latch timing controller 18, and the internal state of the specified part of memory is supplied to a display contents latch unit according to information from an address bus and a bus timing control signal. The display contents latch unit latches the internal state and supplies it to a display device so that the internal state of memory can be identified and debugged.

Abstract: In an information processing debugging apparatus, a debugger owns a debug information adding element and a data with type access instructing element. The debug information adding element gives data type symbol information of a data type from a debug information object file to be used by an information processing program in a program object file to be debugged. The typed data access instructing element instructs an access operation by using a variable symbol of the information process program and an added data type symbol information as a variable having a data type where an operator designates a variable of the information program. Such an information processing program which is not formed by a debug option is symbolically debugged without increasing the memory capacity. A practical information processing program such as a library which is not directly related to debugging operation can also be symbolically debugged.

Abstract: PURPOSE:To provide a parallel program generating method and its generation supporting device which facilitate the test debugging of parallel programs and make the development of the parallel programs efficient, and the parallel program executing device which makes possible partial execution guaranteeing effective test debugging and reproducibility. CONSTITUTION:These devices are equipped with a sequencing means 12 which converts a 1st parallel program having parallel structure into a sequentially executable sequential program, a test debugging means 16 which performs the test debugging of the sequential program and generates test debugging information, a parallelizing means 18 which converts the sequential program after the test debugging into a 2nd parallel program by parallelizing the program based on the test debugging information. Further, the test debugging means 16 includes a means for introducing information regarding parallelism in the sequential program.

Abstract: PURPOSE: To simply and efficiently debugging a software program. CONSTITUTION: In a computer system, information for important debug is read out from a computer memory and/or a remote storing memory. Through the use of this information for debugging, the tree of calling between various functions constituting a program to debug is diagrammatically displayed. A debug command is accepted through a diagrammatic user interface by user's direct operation to the diagrammatic display of the function of the program. The performance of accepting the user command through the diagrammatic user interface and the performance of displaying information for important debug by using this interface facilitate the debug of the program very much. COPYRIGHT: (C)1996,JPO

Abstract: SUMMARY In this paper we describe the design and implementation of an integrated monitoring and debugging system for a distributed real-time computer system. The monitor provides continuous, transparent monitoring capabilities throughout a real-time system’s lifecycle with bounded, minimal, predictable interference by using software support. The monitor is flexible enough to observe both high-level events that are operating system- and application-specific, as well as low-level events such as shared variable references. We present a novel approach to monitoring shared variable references that provides transparent monitoring with low overhead. The monitor is designed to support tasks such as debugging realtime applications, aiding real-time task scheduling, and measuring system performance. Since debugging distributed real-time applications is particularly difficult, we describe how the monitor can be used to debug distributed and parallel applications by deterministic execution replay.

Abstract: Embedded computers (EC) have been used widely, however, embedded computer software is often difficult to develop for the lack of a suitable debugging environment. With the traditional in-circuit debugging method, it is difficult to analyze the reason for errors; also it is impossible to debug a software before the implementation of the associated hardware; moreover, it costs both money and time to create the hardware, so that it can hardly keep up with the ever-changing requirements of a great number of ECs. To tackle the problem, we have researched a prototyping method for a simulation debugging environment (SDE) of embedded computer software. Our purpose is to establish an environment to construct SDE and use the software SDE to substitute the traditional in-circuit debugging environment. By the method, users can construct a SDE at a higher speed and lower cost, the development efficiency for embedded computer software will also be greatly increased.

Abstract: A semiconductor with dedicated wire bond sites that are routed and via'd only to a top surface of a semiconductor package to flush mount pads where they are probed during debug, thus reducing the overall inductance and capacitance of the path from the wire bond site to the debug probing site over conventional debug testing by means of dedicated pins on the semiconductor package. This design permits higher performance debug data capture, while at the same time decreasing the number of pads and pins that are necessary for debug.

Abstract: The background mode of operation for the M68MC16 and M68300 families of microcontrollers has provided a method whereby an external host development system can take control of the microcontroller causing it to execute certain elementary commands. As shown here, a more complex system can be built using the background mode as a base to form an inexpensive, yet capable, emulation system. The addition of a bus state analyzer and appropriate software can further enhance a host development system's usefulness without significantly impacting the complexity of the emulation/debugging system. Most importantly, the background debug mode allows the actual microcontroller in the target system to emulate itself providing, perhaps, the most accurate form of emulation.

Abstract: This specialized hardware assists program debugging and testing and program performance evaluation. It is installed like any other peripheral device.