ATA Packet Interface

Abstract: A storage device made of flash memory module(s) and a storage device controller and a PCI Express interface unit, is implemented to be compatible with (1) either ATA, ATAPI, SCSI or proprietary specification, and (2) PCI Express platform such as, with then, ExpressCard Standard or PCI Express Card Specification or PCI Express Mini Card Specification. The device includes memory module(s), which can accept data transfer and configuration and status report to/from non-volatile solid-state memory herein referred to as flash memory module(s). The storage device controller and the PCI Express interface unit work together to provide (A) PCI Express interface functionality and compatibility, and (B) ATA, ATAPI or SCSI or proprietary programming interface functionality and compatibility, alone with common flash memory operations such as programming reading, writing, erasing, and data transferring from/to PCI Express host platform.

Abstract: A transmission interface compatible with the AT Attachment Packet Interface (ATAPI) that achieves transfer rates greater than those possible with an Integrated Disc Electronics (IDE) bus. The transmission interface includes a transmission ATAPI circuit, a packetizing circuit and a converter. The transmission ATAPI circuit monitors the content of the ATAPI and, when a change is detected, generates a first set of signals representative of that change. The first set of signals are single-ended, parallel to one another and use Transistor-Transistor Logic (TTL) voltage levels. The packetizing circuit packetizes the first set of signals to generate a second set of signals, which representing a packet. The packet payload represents the change in the contents of the ATAPI. The second set of signals are also single-ended, parallel to one another and use TTL voltage levels. The converter converts the second set of signals into a third set of signals and couples these to a serial bus. The third set of signals are serial to one another, and use low voltage level, differential signaling. Thus, the third set of signal are suited for transmission by the serial bus, which includes many fewer wires than available in an IDE bus while operating at a faster data rate.

Abstract: ATA devices, such as mass storage units, have increasingly larger storage sizes that use larger configuration register sizes A command block format allows the USB/ATA bridge circuit to be used with ATA devices with larger registers and at the same time operates with earlier ATA command block formats

Abstract: A method and system for detecting and reporting storage hardware failure prediction is disclosed. The method and system provide a standardized mechanism for any type of storage device to predict and report storage failures. This includes SMART SCSI devices, SMART ATA/ATAPI devices, non-SMART SCSI devices, non-SMART ATA/ATAPI devices, proprietary storage devices, and others such as CD-ROM drives, DVD ROMs, tape drives, and RAM disks. A device driver obtains failure prediction status information and propagates it to a management application. The information may be propagated via a failure prediction filter driver used to perform statistical analysis or proprietary access to the hardware. In a Windows operating environment, information is propagated from the device driver through a Windows Management Instrumentation component. The Windows Management Instrumentation component bridges the gap across user mode and kernel mode, thereby allowing management applications in user mode to obtain information from device drivers residing in kernel mode. A standardized set of APIs is provided for performing storage device failure prediction.