Abstract: Tools to systematically reprogram cellular behavior are crucial to address pressing challenges in manufacturing, environment, or healthcare. Recombinases can very efficiently encode Boolean and history-dependent logic in many species, yet current designs are performed on a case-by-case basis, limiting their scalability and requiring time-consuming optimization. Here we present an automated workflow for designing recombinase logic devices executing Boolean functions. Our theoretical framework uses a reduced library of computational devices distributed into different cellular subpopulations, which are then composed in various manners to implement all desired logic functions at the multicellular level. Our design platform called CALIN (Composable Asynchronous Logic using Integrase Networks) is broadly accessible via a web server, taking truth tables as inputs and providing corresponding DNA designs and sequences as outputs (available at http://synbio.cbs.cnrs.fr/calin). We anticipate that this automated desi...

Abstract: We propose a low area overhead and power-efficient asynchronous-logic quasi-delay-insensitive (QDI) sense-amplifier half-buffer (SAHB) approach with quad-rail (ie, 1-of-4) data encoding The proposed quad-rail SAHB approach is targeted for area- and energy-efficient asynchronous network-on-chip (ANoC) router designs There are three main features in the proposed quad-rail SAHB approach First, the quad-rail SAHB is designed to use four wires for selecting four ANoC router directions, hence reducing the number of transistors and area overhead Second, the quad-rail SAHB switches only one out of four wires for 2-bit data propagation, hence reducing the number of transistor switchings and dynamic power dissipation Third, the quad-rail SAHB abides by QDI rules, hence the designed ANoC router features high operational robustness toward process-voltage-temperature (PVT) variations Based on the 65-nm CMOS process, we use the proposed quad-rail SAHB to implement and prototype an 18-bit ANoC router design When benchmarked against the dual-rail counterpart, the proposed quad-rail SAHB ANoC router features 32% smaller area and dissipates 50% lower energy under the same excellent operational robustness toward PVT variations When compared to the other reported ANoC routers, our proposed quad-rail SAHB ANoC router is one of the high operational robustness, smallest area, and most energy-efficient designs

Abstract: Sense-amplifier half-buffer method with quad-rail (i.e., 1-of-4) data programming is focus about power and Low area Overhead in Low Power applications in asynchronous logic manner. The planned SAHB method is besieged for energy effectual and of asynchronous NoC (Network-On-Chip) planning of router strategy. The foremost characteristics of quad-rail SAHB method is specified as priority manner. The primary one is, quad-rail SAHB is planned to utilize the four ports for Asynchronous Network-On-Chip (NoC) router output way of delivery and here diminishing the total amount of transistors and region area overhead. Secondary one is the SAHB instructs one port away from four ports for two bit data circulation. The digit of transistor switching occurrence and also vivacious power rakishness. Finally, the SAHB combine by Delay Incentive rules, to plan the router attributes lofty functioning sturdiness follow up the temperature-voltage variations. The proposed technique is to execute the ANoC router plan for 18 bit. The benchmark of the projected SAHB- quad-rail ANoC router description to achieve 32% lesser area. The dissipation of energy level is upto 50%.

Abstract: Analyzing the timing properties of asynchronous systems is essential for characterizing their performance and power. Previous work on timing showed that such systems under and-causality and fixed delay exhibit periodicity properties. We give a different graph-based rigorous proof of the exact timing behavior of more general classes of such systems, and conclude their exact periodicity property, where each of the signal transition will occur with the same period after finite occurrences. We established our results under weaker assumption about system connectivity/topology, and this paper provides the theoretical foundation, for the exact periodicity property to be applied and exploited in circuits containing a combination of synchronous and asynchronous components. We provide simulation-based results for several typical asynchronous circuit topologies to quantify this time period in practical circuits. We also provide an extension of our analysis and methods to the case of bounded delay systems. A key result that is a consequence of our analysis is that asynchronous circuits can be integrated with synchronous logic via a metastability-free interface, thereby eliminating the high-overhead synchronizers when an asynchronous circuit is fully surrounded by synchronous logic.

Abstract: Asynchronous logic offers the advantages of no clock tree, robust circuit operation, avoidance of worst-case timing margins, and a reduced emission spectrum. Thus, computational paradigms are sought to attain advantages of clockless logic by leveraging the complementary characteristics of emerging devices and CMOS transistors within novel circuit designs. This paper introduces Spin Torque Enabled NULL Convention Logic (STENCL), which exploits the physical characteristics of non-volatile Domain-Wall (DW) and memristive devices to realize the Quasi-Delay-Insensitive (QDI) NULL Convention Logic (NCL) asynchronous design methodology. First, a formal algorithm is developed to transform NCL-based threshold m-of-n gate realizations to STENCL, in order to generate the corresponding input memristance and NULL module memristance required for nominal currents achieving DW device biasing. Second, hysteresis and set/reset conditions are realized by determining the corresponding current fluctuations required to move the DW within each threshold logic gate to realize all 27 foundational NCL gate structures, which are then simulated to assess energy and delay metrics. Third, a case study of a four-stage pipelined 32-bit IEEE single-precision floating point co-processor implemented as a dual-rail STENCL architecture is compared to a conventional CMOS-based NCL design implemented by an IBM SOI1250 45nm CMOS process. Fourth, a sensitivity analysis is performed to assess the impact of write accuracy and drift on memristor and DW device operation. Results indicate that STENCL-based designs achieve between 2-fold to 20-fold reduction in energy consumption with up to 8-fold reduction in area, over an equivalent CMOS-based NCL design for 32-bit full adders. Comparisons for various four-stage pipelined 32-bit IEEE single-precision floating-point co-processors and ISCAS benchmarks further substantiate those benefits for operation within acceptable tolerances at identical process technology nodes.

Abstract: Asynchronous circuits are becoming increasingly important in system design for Internet of Things, where they orchestrate the interface between big synchronous computation components and the analog environment, which is inherently asynchronous and has high uncertainty with respect to power supply, temperature, and long-term aging effects. However, wide adoption of asynchronous circuits by industrial users is hindered by a steep learning curve for asynchronous control models, such as signal transition graphs (STGs), that are developed by the academic community for specification, verification, and synthesis of asynchronous circuits. In this paper, we introduce a novel high-level description language for asynchronous circuits, which is based on behavioral concepts —high-level descriptions of asynchronous circuit requirements, that can be shared, reused, and extended by users, and can be automatically translated to STGs for further processing by conventional asynchronous and synchronous electronic design automation tools, such as Petrify and Mpsat. Our aim is to simplify the process of capturing system requirements in the form of a formal specification, and to promote behavioral concepts as a means for design reuse. The proposed design flow is fully automated in open-source toolsuite Workcraft, and is applied to the development of an asynchronous power regulator.

Abstract: The complementary roles of asynchronous architecture with nonvolatile spintronic devices are explored herein to realize a novel asynchronous logic element. By redesigning the Muller C-element to take advantage of spintronic device non-volatility and area efficiency, benefits such as reduced asynchronous handshaking area overhead, are achieved in addition to instant on/off capabilities for reduced static-power dissipation through power gating. We propose a novel eight transistor and one spintronic device Muller C-element design which is 20% faster and uses 68% of the power of previous non-volatile Muller C-element designs. This spintronic Muller C-element is demonstrated within a four-phase dual-rail asynchronous pipeline resulting in 48% fewer transistors in comparison with the previous designs. Additionally, bundled-data protocol overhead is shown to be reduced by using the spintronic Muller C-element proposed herein. Detailed analysis of the effects of driving transistor width and the tunneling magnetoresistance ratio on device performance characteristics is included.

Abstract: Multiplication is a basic arithmetic operation that is encountered in almost all general-purpose microprocessing and digital signal processing applications, and multiplication is physically realized using a multiplier. This paper discusses the physical implementation of indicating asynchronous multipliers, which are inherently elastic and are robust to timing, process, and parametric variations, and are modular. We consider the physical implementation of many weak-indication asynchronous multipliers using a 32/28-nm CMOS technology by adopting the array multiplier architecture. The multipliers are synthesized in a semi-custom ASIC-design style. The 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshake protocols are considered for the data communication. The multipliers are realized using strong-indication or weak-indication full adders. Strong-indication 2-input AND function is used to generate the partial products in the case of both RTZ and RTO handshaking. The full adders considered are derived from different indicating asynchronous logic design methods. Among the multipliers considered, a weak-indication asynchronous multiplier utilizing the biased weak-indication full adder is found to be efficient in terms of the cycle time and the power-cycle time product with respect to both RTZ and RTO handshaking. Also, the 4-phase RTO handshake protocol is found to be preferable than the 4-phase RTZ handshake protocol for achieving enhanced optimizations in the design metrics.

Abstract: In this paper we propose a novel tool called Dirmap to the synthesis, by direct mapping, of asynchronous controllers, described by the Extended Signal Transition Graph (XSTG) Specification. The XSTG specification combines the strengths of the XBM specifications and of the STG, while the direct mapping method presents the advantages of simplicity, requiring little computational effort and thus allowing synthesizing large specifications without any knowledge of the asynchronous logic.

Abstract: We have implemented an asynchronous mesh network. This paper describes our innovative design using a Click controller. Compared to designs that use other asynchronous circuit families with C-elements and four-phase bundled data, our two-phase Click-based Bounded Bundled Data design is faster, but introduces phase skews when handling concurrent traffic at a single node. Instead of eliminating the phase skews, we use them as computation slots. Our network uses a novel asynchronous arbiter with a queue that can accept data from both the four cardinal directions as well as from a local source, five directions in all. We have implemented our network design in 1 × 1, 2 × 2 and 4 × 4 sizes, larger network could be implemented easier since the isomorphism and modularity of the routing nodes. Our experiments show that an initial data item passes through a node in 157ns v.s. 81ns for non-delay-branch and delay-branch designs separately. Following items take about 65% as long. But for a network, the average latency of a node keeps almost same for different paths. We believe that with the non-delay-branch designs, our asynchronous mesh network could offer 10.1M routes per second for a 1 × 1 network and 5.33M routes per second for 2 × 2 or 5.06M for 4 × 4 networks, and work at the rate of 17.3M, 10.1M and 11.7M with the enhanced delay-branch way. For both cases, its latency is approximately linear with scale.

Abstract: The present invention provides a reconfigurable convolutional neural network acceleration circuit based on asynchronous logic. The circuit comprises three portions consisting of basic processing elements (PE), a processing array formed by the PEs and a configurable pooling unit. The circuit employs the basic configuration of a reconfigurable circuit to perform reconfiguration of the pressing arrayfor different convolutional neural network models; the circuit is integrally based on the asynchronous logic to employ a lock clock generated by Click units in an asynchronous circuit to replace a global clock in a synchronous circuit and employ an asynchronous pipeline architecture formed by cascading the Click units; and finally, the circuit employs the asynchronous communicating Mesh network to achieve data reuse to reduce power dissipation through reduction of the number of times of accessing the memory. The circuit provided by the invention is flexible and high in degree of parallelism and data reuse rate, and has a power consumption advantage compared to an acceleration circuit implemented through synchronous logic so as to greatly improve the processing speed of the convolutional neural network in the low power consumption.

Abstract: The conventional approach to logic design targeting LUTs of limited inputs number is oriented on multi-level decomposition. Nowadays reconfigurable chips contain multiple LUTs that can be combined. It implies producing LUT-based structure of various inputs number to match design needs. As a result, a function can be implemented using one-level LUT which increases circuit performance. In the paper, asynchronous dual-rail logic function design targeting LUT of minimal size (number of inputs) is proposed. It is based on conventional Sum-Of-Product terms (SOP) functions what is in contrast to existing methods where Sum-Of-Minterms (SOM) and Disjoint SOP representations are considered. It is shown, that LUT architectural features and delays ensure SOP hazard-free implementation. Although SOP representation reduces LUT size, existing methods and tools producing SOP (for example, Espresso) are primary oriented on product term minimization. In the paper, the method of generating SOP targeting literal number minimization is proposed. Within this method, efforts are focused on literal (rather that product term) minimization. The task is formulated as a unate covering problem. A heuristic algorithm to solve the problem is proposed. Two sets of benchmarks are processed and comparison of SOM and SOP implementations is done. Using our method, improvement w.r.t. LUT size is achieved.

Abstract: The increasingly complex digital integrated circuits (ICs) often incorporate multiple power domains, thereby requiring multiple voltage converters to produce the corresponding supply voltages. These converters not only take substantial on-chip layout area or off-chip space, but also aggregate the power loss during the voltage conversions. In order to alleviate this problem by reducing the number of voltage converters needed, an asynchronous Multi-Threshold NULL Convention Logic (MTNCL) “stacked” circuit architecture is presented in this paper. By stacking multiple MTNCL circuits between power and ground, multiple of $V_{DD}$ can be supplied to the entire stack. With simple control mechanisms, the dynamic range fluctuation problem can be mitigated. A 130nm Bulk CMOS process and a 32nm SOI CMOS process are used to evaluate the effect of stacking different circuitry while running different workloads. Results and physical implementations are discussed for demonstrating the feasibility and advantages of the proposed MTNCL stacking architecture.

Abstract: This paper presents a power management circuit for RF energy harvesting via transplanting a single inductor dual output (SIDO) boost converter and introducing a two-way energy supply policy. The power management circuit can achieve self-power operation, load discontinuous operation, and fast starting up. Moreover, the power conversion efficiency is improved via not only using fractional open circuit voltage maximum power point tracking to harvest as much energy as possible, but also adopting asynchronous logic to reduce the intrinsic power loss. Finally, the power management circuit is verified in CSMC 0.18µm CMOS process.

Abstract: Asynchronous circuits are pervasive in modern synchronous systems, but they are still designed and verified in isolation, using dedicated asynchronous design flows, formalisms and tools We describe a method to verify gate-level asynchronous circuit implementations using formal verification tools and property languages for synchronous logic We report observations and findings from applying this method to use case designs using an industrial and an open source formal verification tools for synchronous logic, and compare performance and verification capabilities against two verification tools for asynchronous circuits Finally, we discuss the advantages and practical considerations of bridging synchronous logic verification tools to the domain of asynchronous circuits Our main conclusion is that, while there are performance penalties, there is still significant value in enabling users to verify asynchronous circuits using tools that may be more familiar, trusted or more widely adopted

Abstract: Synchronous Finite State Machines (SFSM) are widely used in the control unit design of complex digital systems. These systems are implemented in CMOS DSM (Deep-Sub-Micron) technology and can present serious problems related to the global clock. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, despite of the difficulties of the application of asynchronous logic. This paper proposes a new state assignment method for Asynchronous FSMs, which is described by the popular specification known as Extended Burst-Mode (XBM). The state assignment method uses the two-hot code to encode the XBM_AFSMs. Also, the paper proposes a “necessary and sufficient” condition for XBM_AFSMs encoded in two-hot to be synthesized with conventional tools, in the steps of logic minimization and technology mapping. Doing a comparison for a set of fifteen benchmarks with AFSMs of local clock that use the conventional logical minimization, the proposed method obtained an average reduction of products of 23% and literals of 51%.

Abstract: Due to plenty of intrinsic overheads in synchronous circuit design, asynchronous designs have drawn consideration in the Electronic Design Automation Industry. In an asynchronous logic design methodologies, Null Convention Logic is the best delay-insensitive logic as it has many advantages such as inherent robustness, power consumption, and modular reusability. For digital signal processing and computational dynamic range applications, floating point multiplication is a critical part with high precision and low power. Null cycle reduction technique and fine grain pipelining can be applied to the Null Convention Logic floating point multiplier to increase throughput. In this paper, Multiplier using Asynchronous Delay-Insensitive single precision NCL Floating Point Multiplier with IEEE-754 standard architecture is proposed and its performance is compared with different topologies in terms of various metrics such as delay, area, power consumption, and percentage of energy savings.

Abstract: This chapter covers basic components of synchronous sequential logic, D flip-flop, T flip-flop, J-K flip-flop, register, analysis of sequential logic, state diagram, flip-flop excitation table, and how to design a counter.

Abstract: This brief presents a parallel single-rail self-timed adder. It is based on a recursive formulation for performing multibit binary addition. The operation is parallel for those bits that do not need any carry chain propagation. Thus, the design attains logarithmic performance over random operand conditions without any special speedup circuitry or look-ahead schema. A practical implementation is provided along with a completion detection unit. The implementation is regular and does not have any practical limitations of high fanouts. A high fan-in gate is required though but this is unavoidable for asynchronous logic and is managed by connecting the transistors in parallel. Simulations have been performed using an industry standard toolkit that verify the practicality and superiority of the proposed approach over existing asynchronous adders

Abstract: In today’s world there is a great need for low power design and area efficient high performance in DIP (Digital Image Processing) system. In this paper the proposed method presents a parallel single-rail self-timed adder. It uses recursive method for performing multi bit binary addition. This design attains good performance without any special speedup circuitry. A practical implementation is provided along with a completion detection unit. The implementation is regular and does not have any practical limitations of high fan outs. The recursive method based adder consumes least power among other Self-timed adders. In our work this can be reduced with proposed adder. This technique presents a pre-processing and post processing adder to minimize the multiplier technique. A high fan-in gate is required though but this is unavoidable for asynchronous logic and is managed by connecting the transistors in parallel. Simulations have been performed using cadence tool and superiority of the proposed approach over existing asynchronous adders. In this proposed system we are using a parallel prefix adder it is used to reduce the power consumption, area efficiently.

Abstract: In this paper, an 8-bit asynchronous wave-pipelined arithmetic logic unit has been modified with set of 8 arithmetic and 12 logical operations. All the internal modules have been modified in order to reduce power and latency by using ASIC semi-custom design flow in cadence® environment using gpdk-180-nm technology. This modified design has achieved reduction in power by 45%, reduction in delay by 19%, reduction in area by 43%, reduction in cell count by 49% as compared to the existing ALU.

Abstract: The invention provides an extensible general function level asynchronous circuit which comprises a configuration module, a selection logic module, at least two synchronous logic modules and at least two function logic modules connected with the synchronous logic modules in a one-to-one corresponding mode; Due to the fact that existing clock source level switching and synchronous method switching are function module level switching and synchronizing, and the problems of a circuit structure adopting direct clock source switching and instability caused by direct clock switching are solved; meanwhile, by adopting function module level extension, control switching and clock selection logic can be conveniently changed.

Abstract: The designs of an asynchronous dual-rail domino logic (DRDL) and the conventional CMOS logic under near-threshold operation are compared. The delay time and energy consumption of an 8-bit full adder pipeline are simulated using HSPICE with 180-nm CMOS technology. The results show that, considering process variations, DRDL is faster than CMOS below 1.1 V. The delay performance of DRDL at 0.25 V is equivalent to that of CMOS at 0.4 V, while the energy-delay product of DRDL is 40% smaller than that of CMOS.

Abstract: The invention discloses a device for realizing bus protocol asynchronous logic circuits of embedded processors, and aims at converting access temporal logics of the embedded processors into ahb-bus bus access protocols of a standard AMBA. The device comprises an embedded processor, a bus protocol asynchronous logic module and an AMBA module, wherein the embedded processor, the bus protocol asynchronous logic module and the AMBA module are controlled by a same clock; and when a data bit width of a bus of the embedded processor and a data bit width of an ahb-bus bus of the AMBA module are mutually in a multiple relationship, data exchange between the cross-clock domain embedded processor and a system bus can be processed, and more bit width data buses can be used to transmit more data at thesame time under a same clock frequency, so as to improve the bandwidth performance. According to the device, an interface problem of uniformly accessing external equipment by specific embedded processors is solved, namely, the aim of general access is realized via relatively few logic circuit resources.

Abstract: In order to make full use of the advantages of single photon detection capability of Microchannel plate detectors (MCP), a front-end readout circuit with high dynamic range is designed in this paper. The multiple charge transfer logic, inspired by asynchronous logic successive approximation ADC, is used to extend the dynamic range. The readout circuit mainly includes the dynamic range expansion module, the buffer module, the high-speed comparator module, and the time digital conversion module. It can not only provide ultra-wide input signal dynamic range, but also obtain high-precision time and space resolution.

Abstract: Purpose Power consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits. Design/methodology/approach In this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment. Findings Experimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits. Originality/value The proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.

Abstract: The invention discloses a bus protocol conversion bridging device applied to embedded processors, and aims at converting access temporal logics of the embedded processors into ahb-bus bus access protocols of a standard AMBA. The device comprises an embedded processor, a bus bridging logic module and an AMBA module, wherein the embedded processor, the bus protocol asynchronous logic module and theAMBA module are controlled by a same clock; and when a data bit width of a bus of the embedded processor is consistent with a data bit width of an ahb-bus bus of the AMBA module, delay of a clock introduced by the bus bridging logic module is zero. According to the device, an interface problem of uniformly accessing external equipment by specific embedded processors is solved, namely, the aim of general access is realized via relatively few logic circuit resources.