Abstract: Future many cores, either for high performance computing or for embedded applications, are facing the power wall, and cannot be scaled up using only the reduction of technology nodes; 3D integration, using through silicon via (TSV) as an advanced packaging technology, allows further system integration, while reducing the power dissipation devoted to system-level communication In this paper, we present a 3D modular and scalable network-on-chip (NoC) architecture implemented using robust asynchronous logic The 3DNOC circuit targets a Telecom long-term evolution application; it is composed of two die layers, fabricated in 65 nm technology using TSV middle aspect ratio 1:8, and integrates ESD protection, a 3D design-for-test, and a fault tolerant scheme The 3D links achieve 066 pJ/b energy consumption and 326 Mb/s data rate per pin for the parallel link Thin die effect is demonstrated by thermal analysis and measurements, as well as the dynamic self-adaptation of the 3D link performances with 3D thermal conditions Finally, the scalability of the 3DNOC circuit, in terms of power delivery network and thermal dissipation, is demonstrated by using simulations up to a 3D stack of eight die layers

Abstract: Clocking of electrical circuit is a crucial issue since clock signal is used to establish the flow-of-time inside electronic world Before, during and after the "Moore's law", flow-of-time is an eternal issue Alongside processor, memory/storage and analog/ RF technologies, IC clocking could be regarded as the 4th major IC design technology In the past several decades, clock is mostly used in the form of fixed-frequency with high frequency stability For future system, however, this type of clock signal is not sufficient because its usage environment is not expected to be stationary but dynamic To meet this challenge, innovation in IC clocking is required This paper first discusses the difficulties in creating flow-of-time; then the two long-lasting problems in clock generation are identified, and then new challenges in the design of future system are summarized Afterwards, the Time-Average-Frequency based flexible clock generator is introduced and its potential to confront these challenges is addressed Several major issues in modern design are discussed The paper concludes with a vision that, for electronic system to improve its information processing efficiency to next level, clock technology is the next frontier to be explored

Abstract: As clock skew and power consumption become major challenges in deep submicron design of synchronous circuits, asynchronous designs, especially Null Convention Logic (NCL) subset, is gaining more and more attention. The NCL methodology eliminates problems related to the clock tree and also, can significantly reduce power consumption, noise and electromagnetic interference (EMI). In this paper, we present a comprehensive introduction to the NCL design approach, from fundamentals to recent advances. In addition, automated design flows for NCL circuits are also discussed.

Abstract: Reliability is one of the principal characteristics in the design of many systems. Logic circuits are one of them. These systems are very interesting objects from the reliability point of view, because they have some characteristics that are not very common in classical approaches used in reliability engineering. First, their activity depends not only on the operability of its components (logic gates), but also on other influences, which are represented by values of the circuit input signals. Second, logic circuits are typical instances of noncoherent systems. We propose a new method of computing circuit availability (unavailability) and several measures for investigation of topological properties of a logic circuit. These measures allow us to detect components (logic gates) with the greatest influence on the circuit operability. The method is based on using the methodology of Boolean differential calculus. All the approaches presented in this paper are illustrated using the example of reliability analysis of a one-bit full adder.

Abstract: Locking Segment Insertion Bits (LSIBs) have been proposed to secure access to on-chip embedded instruments in IEEE 1687 networks LSIBs can be opened (or closed) only if the correct key value is applied to the LSIB's key logic circuit Using gate-level simulations previously used for cryptographic circuits, we evaluate the susceptibility of several LSIB key logic designs to simple power analysis attacks We show that the key logic may be susceptible to simple power analysis attacks when the key logic for each LSIB is separate However, sharing the key logic among multiple LSIBs mitigates simple power analysis attacks Sharing key logic circuits among four LSIBs gave an average coefficient of determination of 005 between the circuit’s switching activity and the key bit values as compared to an average coefficient of determination value of 054 for single LSIBs Furthermore, this reduced the scan cell overhead for LSIBs by a factor of four

Abstract: Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of complex digital systems. These systems can present serious problems related to the global clock. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, despite of the difficulties of the application of asynchronous logic. An interesting architecture for the Asynchronous Finite State Machines (AFSM) is based on local clock, because it reduces the requirements of asynchronous logic. This manuscript proposes a novel architecture of local clock for AFSMs, which is described by a popular specification known as Extended Burst-Mode (XBM). This architecture presents a better latency time when compared with other local clock architectures. Furthermore, the manuscript proposes a “necessary and sufficient” condition for local clock AFSMs to be synthesized completely on the proposed architecture by using only conventional tools. Through a case study, we present the architecture, its robustness, the synthesis procedure and a comparison with other local clock architectures, highlighting its advantages.

Abstract: Internet of Things (IoT) devices are always having low power budget and high security demands. This paper describes the design and results of fabricated Advanced Encryption Standard (AES) chip in UMC 130 nm CMOS technology by using Faraday standard cells. The AES core is designed in fully QDI asynchronous circuit style. The core ciphers 128-bit data/key in 300 ns and consumes 5.47 mW.

Abstract: One of the popular methods of asynchronous logic implementation is based on so called Delay-Insensitive-Minterm-System (DIMS), where a sum-of-minterms (SOM) function is given and each minterm is represented using a state-holding (C-) element. However, such implementation is rather expensive since minterm minimization is not allowed. In the paper, structure called factorized DIMS is proposed. It is shown that under realistic delay limitation, instead of SOM, strong indication can be ensured for the sum of mutually orthogonal product terms resolved into factorized form. It reduces significant implementation complexity.

Abstract: With the continuous scaling down of technology in the field of integrated circuit design, low power dissipation has become one of the primary focuses of the research. With the increasing demand for low power devices, adiabatic logic gates prove to be an effective solution. This paper briefs on different adiabatic logic families such as ECRL (Efficient Charge Recovery Logic), 2N-2N2P and PFAL (Positive Feedback Adiabatic Logic), and presents a new proposed circuit based on the PFAL logic circuit. The aim of this paper is to simulate various logic gates using PFAL logic circuits and with the proposed logic circuit, and hence to compare the effectiveness in terms of average power dissipation and delay at different frequencies. This paper further presents implementation of C17 and C432 benchmark circuits, using the proposed logic circuit and the conventional PFAL logic circuit to compare effectiveness of the proposed logic circuit in terms of average power dissipation at different frequencies. All simulations are carried out by using HSPICE Simulator at 65 nm technology at different frequency ranges. Finally, average power dissipation characteristics are plotted with the help of graphs, and comparisons are made between PFAL logic family and new proposed PFAL logic family.

Abstract: This page proposed a simple light control circuit which designed by using power supply circuit, sonic circuits, electric circuit and delay circuit four parts. The main chip for CD4011, have inside of the four and to complete the sonic or circuit, electric, delay logic circuit. During the day, no matter how much a pedestrian voice, is ever shine light bulb. Dark night, circuit in a body to make the microphone as long as testing noise, and will automatically be bright for pedestrians lighting, several minutes after the automatic and put out, effective energy saving. Applicable scope and the working principle of the circuit principle diagram and given device parameters selection, power saving effect is obvious, at the same time greatly reduce the maintenance quantity, saving money, use effect is good.

Abstract: NULL Convention Logic (NCL) is a promising design paradigm for constructing low-power robust asynchronous circuits. The conventional NCL paradigm requires pipeline registers for separating two neighboring logic blocks, and those registers can account for up to 35% of the overall power consumption of the NCL circuit. This brief presents the Register-Less NCL (RL-NCL) design paradigm, which achieves low power consumption by eliminating pipeline registers, simplifying the control circuit, and supporting fine-grained power gating to mitigate the leakage power of sleeping logic blocks. Compared with the conventional NCL counterpart, the RL-NCL implementation of an 8-bit five-stage pipelined Kogge–Stone adder can reduce power dissipation by 56.4%–72.5% for the input data rate ranging from 10 to 900 MHz. Moreover, the RL-NCL implementation can reduce the transistor count of the adder by 49.5%.

Abstract: Formal verification of asynchronous circuits is known to be challenging due to highly non-deterministic behavior exhibited in these systems. One of the main challenges is that it is very difficult to come up with a systematic approach to establishing invariance properties, which are crucial in proving the correctness of circuit behavior. Non-determinism also results in asynchronous circuits having a complex state space, and hence makes the verification task much more difficult than in synchronous circuits. To ease the verification task by reducing non-determinism, and consequently reducing the complexity of the set of execution paths, we impose design restrictions to prevent communication between a module M and other modules while computations are still taking place that are internal to M. These restrictions enable our verification framework to verify loop invariants efficiently via induction and subsequently verify the functional correctness of asynchronous circuit designs. We apply a link-joint paradigm to model asynchronous circuits. Our framework applies a hierarchical verification approach to support scalability. We demonstrate our framework by modeling and verifying the functional correctness of a 32-bit asynchronous serial adder.

Abstract: We propose efficient algorithms to construct a low-power clock tree for through-silicon-via (TSV)-based 3D-ICs. We use shutdown gates to save clock trees’ dynamic power, which selectively turn off certain clock tree branches to avoid unnecessary clock activities when the modules in these tree branches are inactive. While this clock gating technique has been extensively studied in 2D circuits, its application in 3D-ICs is unclear. In 3D-ICs, a shutdown gate is connected to a control signal unit through control TSVs, which may cause placement conflicts with existing clock TSVs in the layout due to TSV’s large physical dimension. We develop a two-phase clock tree synthesis design flow for 3D-ICs: (1) 3D abstract clock tree generation based on K-means clustering and (2) clock tree embedding with simultaneous shutdown gates’ insertion based on simulated annealing (SA) and a force-directed TSV placer. Experimental results indicate that (1) the K-means clustering heuristic significantly reduces the clock power by clustering modules with similar switching behavior and close proximity, and (2) the SA algorithm effectively inserts the shutdown gates to a 3D clock tree, while considering control TSV’s placement. Compared with previous 3D clock tree synthesis techniques, our K-means clustering-based approach achieves larger reduction in clock tree power consumption while ensuring zero clock skew.

Abstract: This paper presents a novel method to identify and insert redundant logic into a combinational circuit to improve its fault tolerance without having to replicate the entire circuit as is the case with conventional redundancy techniques. In this context, it is discussed how to estimate the fault masking capability of a combinational circuit using the truth-cum-fault enumeration table, and then it is shown how to identify the logic that can introduced to add redundancy into the original circuit without affecting its native functionality and with the aim of improving its fault tolerance though this would involve some trade-off in the design metrics. However, care should be taken while introducing redundant logic since redundant logic insertion may give rise to new internal nodes and faults on those may impact the fault tolerance of the resulting circuit. The combinational circuit that is considered and its redundant counterparts are all implemented in semi-custom design style using a 32/28nm CMOS digital cell library and their respective design metrics and fault tolerances are compared.

Abstract: Quantum-dot Cellular Automata (QCA) has emerged as a new design paradigm for nanotechnologies. Since the operational logic in QCA is the majority logic, much research about the synthesis and optimisation of majority logic has been proposed recently. In this paper, we propose an optimisation method by merging nodes in the Majority-Inverter-Graph, which is the representation of majority logic circuits. Instead of using satisfiability solvers, our approach can identify the node mergers by using logic implications for circuit size reduction. The experimental results show that for a set of EPFL benchmarks, our approach can minimise the node count by 21% when integrated with the state-of-the-art on average.

Abstract: Clock gating is a useful technique to reduce power consumption of a synchronous sequential circuit. Conventionally, we use activity patterns, which are derived from a scheduled data flow graph and a module binding solution, to represent enable logics for clock gating. Based on activity patterns of modules, previous works utilize AND gates to construct activity-driven clock trees. In this paper, we demonstrate that, if we utilize OR gates at the bottom level, the power consumption at higher levels can be greatly reduced. From this observation, we propose a novel activity-driven clock tree design methodology, including a new tree structure and a corresponding design flow. Benchmark data show that our methodology can reduce 7.1% clock power consumption.

Abstract: Quantum dot cellular automata (QCA) is an upcoming nano-technology for its high speed and low power operation in the field of nano-science and nano-electronics. As QCA overcomes the drawbacks of CMOS technology, it has appreciable applications in quantum computation. There are thousands of designs of different logical circuits using QCA but there is no hazard free design of the logical circuits in the field of QCA. In a circuit, hazards always produce an unpredictable output which can be avoided. In this paper, both hazardous and hazard-free asynchronous sequential circuits are considered and compared in terms of kink energy. It is shown that hazard free asynchronous circuit performs better in terms of kink energy in the field of QCA.

Abstract: This paper comments on "Asynchronous Logic Implementation Based on Factorized DIMS" [Journal of Circuits, Systems, and Computers, vol. 26, no. 5, 1750087: 1-9, May 2017] with respect to two main problematic issues: i) the gate orphan problem implicit in the factorized DIMS approach discussed in the referenced article which affects its strong-indication, and ii) how the enumeration of product terms to represent the synthesis cost is skewed in the referenced article because the logic expression contains sum of products and also product of sums. It is observed that the referenced article has not provided a general logic synthesis algorithm excepting only an example illustration involving a 3-input AND logic function. The absence of a general logic synthesis algorithm would make it difficult to reproduce the research described in the referenced article. Moreover, the example illustration in the referenced article describes an unsafe logic decomposition which is not suitable for the multi-level synthesis of strong-indication asynchronous circuits. Further, a logic synthesis method which safely decomposes the DIMS solution to synthesize multi-level strong-indication asynchronous circuits is available in the existing literature, which was neither cited nor taken up for comparison in the referenced article, which is another drawback. Subsequently, it is concluded that the referenced article has not advanced existing knowledge in the field but on the contrary, has caused confusions. Hence, in the interest of readers, this paper additionally highlights some important and relevant literature which provide valuable information about robust asynchronous circuit synthesis techniques which employ delay-insensitive codes for data representation and processing and the 4-phase return-to-zero handshake protocol for data communication.

Abstract: Purpose The purpose of this paper is to present a single-precision floating-point multiplier where a low-power operation is attained through the reduction of switching activity. A floating-point multiplier is the basic building block for many applications such as digital signal processing (DSP) processors and multimedia applications involving a large dynamic range. Design/methodology/approach A floating-point multiplier was implemented in asynchronous logic such as multi-threshold null conventional logic and the proposed multi-threshold dual spacer dual rail delay insensitive logic (MTD3L). The proposed logic deals with high performance and energy efficiency. Findings The Institute of Electrical and Electronics Engineering (IEEE) has provided a standard to define the floating-point representation, which is known as the IEEE 754 standard. Rounding has not been implemented because it is not suitable for high-precision applications. Originality/value The performance aspects of the proposed asynchronous MTD3L floating-point multiplier are obtained using a Mentor Graphics tool and are compared with those of the existing asynchronous logic.

Abstract: A synchronization solution is described, which, in one aspect, allowed finer grained segmentation of clock domains on a chip. This solution incorporates computation into the synchronization overhead time and is called Gradual Synchronization. With Gradual Synchronization as a synchronization method, the design space of a chip could easily mix both asynchronous and synchronous blocks of logic, paving the way for wider use of asynchronous logic design.

Abstract: Designing VLSI circuit using dynamic logic is one of the most area efficient techniques. However, the performance of the dynamic logic is not so promising due to longer time delay and higher leakage power. This research proposes a new model of dynamic logic by incorporating nMOS based resistive gate circuit. The proposed circuit reduces the contention time delay and the leakage power. Extensive simulation results using LTSpice tools demonstrate the validity and superiority of the proposed circuit.

Abstract: The power density of integrated circuits increases with the technology scaling, so the need of implementing low-power designs is increasing. The clock gating technique is typically employed to reduce the dynamic power consumption in digital integrated circuits. However, the use of this approach could affect the reliability of the device in the presence of soft errors caused by radiation. The objective of this work is to propose a methodology in order to find the susceptibility to single event effects of clock-gated designs using the standard design flow for standard cell ASIC. A novel fault injection structure was developed for clock-gated flip-flops. A case study 10-bit counter circuit is used to apply the proposed methodology. Gate-level simulations are performed for the analysis of susceptibility, using the generated netlist along with the delays extracted from the logic synthesis.

Abstract: This paper proposes an integrated shift register circuit for an in-cell touch panel that is robust over clock noises. It is composed of 10 thin film transistors and 1 capacitor, and the time division driving method is adopted to prevent the negative effect of display signals on the touch sensing. Two pre-charging nodes are employed for reducing the uniformity degradation of gate pulses over time. In particular, the proposed circuit connects a drain of the first pre-charging node's pull-up thin film transistor (TFT) to the positive supply voltage instead of clock signals. This facilitates to lower coupling noises as well as to clock power consumption. The simulation program with an integrated circuit emphasis is conducted for the proposed circuit with low temperature poly-silicon TFTs. The positive threshold voltage that shifts up to 12 V at the first pre-charging pull-up TFT can be compensated for without the uniformity degradation of gate pulses. For a 60-Hz full-HD display with a 120-Hz reporting rate of touches, the clock power consumption of the proposed gate driver circuit is estimated as 7.13 mW with 160 stages of shift registers. In addition, the noise level at the first pre-charging node is lowered to −28.95 dB compared with 2.37 dB of the previous circuit.

Abstract: The motivation for this paper is the analysis of input conditions that cause a short-circuit in a logic circuit, that is, that create a direct path from the power supply to ground. We model the logic circuit as a graph where edges represent transistors which are either open or closed, function of the input conditions. From this graph we derive a Quantified Boolean Formula (QBF) problem whose solution identifies the existence of a valid input combination that creates a path in the graph between the pair of nodes that represent the power source and ground, without ever enumerating all input combinations. We build the QBF problem incrementally, minimizing the number of active nodes and hence of possible states. In the end, we obtain a relatively simple CNF expression, function only of the circuit inputs, that is handled by a generic SAT solver. We present results that demonstrate the practical applicability of our method on circuit instances that are intractable by alternative methods.

Abstract: This paper presents a new adiabatic circuit based on the 2-Phase Clocked CMOS Adiabatic Logic (2PC2AL). By adding two logic switches between the power supply and charging-discharging transistor, it can prevent the floating of the nodes and avoid unnecessary energy loss. In this paper, we apply the proposed adiabatic logic circuit to a 4×4-bit multiplier in the LTspice by using a 0.18 µm standard CMOS process. The simulation results show that the function of circuits can be realized and the power consumption can be reduced greatly compared to the CMOS circuit when the frequency ranges from 100 Hz to 100 MHz.

Abstract: The qubit method and hardware/software implementations of parallel synthesis of tests for black box logic defined by Q-coverage are represented. A theoretical background of methods application for a wide class of digital circuits implemented in programmable logic devices is given.

Abstract: Asynchronous quasi-delay-insensitive (QDI) circuits are a promising solution for coping with aggressive process variations faced by modern technologies, as they can gracefully accommodate gate and wire delay variations. Furthermore, due to their inherent robustness, such circuits are also promising for deep voltage scaling applications, where delays are orders of magnitude larger. However, QDI design has an Achilles heel, which is its associated area and power overhead penalties. These can hamper the adoption of this kind of design in current and future technologies. A recently proposed asynchronous circuit design template, the Sleep Convention Logic (SCL), does reduce these overheads significantly. SCL is an enhancement of the Null Convention Logic, a well-known asynchronous circuit QDI design template. This paper analyzes the architecture of circuits based on SCL, identifies and models associated timing constraints that were not described before. The paper also shows experimentally that respecting such constraints is fundamental to guarantee correct operation of these circuits, especially under low voltage supplies.

Abstract: In VLSI technology, designers main concentration were on area required and on performance of the device. In VLSI design power consumption is one of the major concerns due to continuous increase in chip density and decline in size of CMOS circuits and frequency at which circuits are operating. By considering these parameter logical circuits are designed using quaternary voltage mode logic and quaternary current mode logic. Power consumption required for quaternary voltage mode logic is 51.78 % less as compared to binary . Area in terms of number of transistor required for quaternary voltage mode logic is 3 times more as compared to binary. As quaternary voltage mode circuit required large area as compared to quaternary current mode circuit but power consumption required in quaternary voltage mode circuit is less than that required in quaternary current mode circuit .

Abstract: An Ultra Low Voltage (ULV) digital circuit includes a logic circuit comprising a plurality of logic gates and a plurality of buffered interconnects for connecting between the plurality of logic gates, a temperature sensor configured to detect a temperature of the logic circuit, and a voltage controller configured to control a driving voltage provided to the logic circuit in order to reduce a power consumption of the logic circuit based on the detected temperature. Each of the plurality of logic gates and buffered interconnects reduces a signal delay as a temperature increases.