Abstract: Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design techniques, such as wavefront steering and Multi-Threshold CMOS (MTCMOS) for NCL, are discussed. The book culminates with a comprehensive design example of an optimized Greatest Common Divisor circuit. Readers should have prior knowledge of basic logic design concepts, such as Boolean algebra and Karnaugh maps. After studying this book, readers should have a good understanding of the differences between asynchronous and synchronous circuits, and should be able to design arbitrary NCL circuits, optimized for area, throughput, and power. Table of Contents: Introduction to Asynchronous Logic / Overview of NULL Convention Logic (NCL) / Combinational NCL Circuit Design / Sequential NCL Circuit Design / NCL Throughput Optimization / Low-Power NCL Design / Comprehensive NCL Design Example

Abstract: Elasticity in circuits and systems provides tolerance to variations in computation and communication delays. This paper presents a comprehensive overview of elastic circuits for those designers who are mainly familiar with synchronous design. Elasticity can be implemented both synchronously and asynchronously, although it was traditionally more often associated with asynchronous circuits. This paper shows that synchronous and asynchronous elastic circuits can be designed, analyzed, and optimized using similar techniques. Thus, choices between synchronous and asynchronous implementations are localized and deferred until late in the design process.

Abstract: In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

Abstract: As Globally Asynchronous Locally Synchronous (GALS) systems are becoming preponderant in complex SoC and NoC, we present the design and implementation of a new GALS adapter to be used in ANoC, an asynchronous NoC architecture. The proposed GALS adapter is a complete IP integration module, including a new FIFO based design using a Johnson-encoding principle for timing domains interfacing, and a local programmable clock generator for the IP unit. The GALS adapter has been implemented in a ST 65nm technology in standard-cell based design. It is provided as a hard-macro for easy IP integration, can generate 256 clock frequencies from 25 MHz to 1 GHz, and achieves 500 MHz nominal throughput from a clocked domain to a QDI asynchronous logic NoC.

Abstract: A power supply apparatus and method of regulating is provided. A clock generator circuit is configured for generating a clock signal at a predetermined frequency. An amplifier circuit is coupled with the clock generator circuit. The amplifier circuit includes a gain circuit coupled with the clock generator circuit. The amplifier circuit is configured to receive the clock signal at a switching element of the gain circuit. A controller circuit is configured for receiving a modulated error signal of the amplifier circuit and is configured for generating a pulse width modulated signal for controlling a duty cycle of the switching circuit. The switching circuit is configured for receiving the modulated error signal. The error signal is modulated using the clock signal to vary a gain value of the gain circuit according to the predetermined frequency. An output circuit is coupled with the switching circuit and is configured for generating a regulated voltage signal. The controller circuit uses the modulated error signal to substantially reduce harmonic distribution in a switching frequency of the switching circuit. Harmonic distribution in the switching circuit can be reduce by 10.0 db or greater.

Abstract: Utilizing an application specific integrated circuit (ASIC) with 140 different shift chains, and a wide variety of test modes, a design of experiments (DOE) approach was used to characterize a commercial 90 nm CMOS technology for its sensitivity to single event effects (SEE). The variables characterized included: well structure on the wafer, density of well contacts, logic data pattern, angle of indicence, flip-flop redundancy, variation in sensitive node spacing, and the effect of transients as a function of combinatorial logic type. Analysis of the cross section contribution from the clock, flip-flop and SET target circuitry showed that any hardening technique used in a production integrated circuit may be limited in its effectiveness due to other circuits and logic in the integrated circuit.

Abstract: A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.

Abstract: A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.

Abstract: Data-pre-charged dynamic logic, also known as data-driven dynamic logic (D3L), is very efficient when low-power constraints are mandatory. Differently from conventional dynamic domino logic, which exploits a clock signal, D3L uses a subset of the input data signals for pre-charging the dynamic node, thus avoiding the clock distribution network. Power consumption is significantly reduced, but the pre-charge propagation path delay affects the speed performances and limits the energy-delay product (EDP) improvements. This study presents a new dynamic logic named split-path D3L (SPD3L) that overcomes the speed limitations of D3L. When applied to a 16 times 16 bit booth multiplier realised with STMicroelectronics 65 nm IV CMOS technology, the proposed technique leads to an EDP 25 and 30% lower than standard dynamic domino logic and conventional D3L counterparts, respectively.

Abstract: With clock rates beyond 1 GHz, the model of a system wide synchronous clock is becoming difficult to maintain; therefore, asynchronous design styles are increasingly receiving attention. While the traditional synchronous design style is well-proven and backed up by a rich field experience, comparatively little is known about the properties of asynchronous circuits in practical application. In the face of increased transient fault rates, robustness is a crucial property, and from a conceptual view, the so-called ldquodelay-insensitiverdquo asynchronous design approaches promise to be more robust than synchronous ones, since their operation does not depend on tight timing margins, and data are two-rail coded. A practical assessment of asynchronous designs in fault-injection (FI) studies, however, can rarely be found, and there is a lack of adequate methods and tools in this particular domain. Therefore, the objective of this work is 1) to provide a common approach for efficient and accurate FI in synchronous and in asynchronous designs, and 2) to experimentally compare the robustness of both synchronous and asynchronous designs. To this end, a synchronous 16-bit processor as well as its asynchronous (delay insensitive) equivalent are subjected to signal flips and delay faults. The results of over 489 million experiments are summarized and discussed, and a detailed discussion on the specific properties of the chosen asynchronous design style is given.

Abstract: Methods and apparatuses to optimize integrated circuits by identifying functional modules in the circuit having similar functionality that can share circuit resources and producing a modified description of the circuit where the similar functional modules are folded onto common circuit resources and time-multiplexed using an original system clock or a fast clock.

Abstract: A DLL includes a first variable delay circuit that variably delays a first transition of an external signal, a second variable delay circuit that variably delays a second transition of the external signal, a synthesis circuit that synthesizes output signals of the first variable delay circuit and the second variable delay circuit, a duty change detection circuit that changes and detects the duty of an output signal of the synthesis circuit, and delay control circuits that vary the delay of the first variable delay circuit or the second variable delay circuit in accordance with the result of duty detection by the duty change detection circuit.

Abstract: This paper is a survey paper presenting what the author sees as two major and promising trends in the current research in CAD-tools and design-methods for asynchronous circuits. One branch of research builds on top of existing asynchronous CAD-tools that perform syntax directed translation, e.g. the Haste/TiDE tool from Handshake Solutions or the Balsa tool from the University of Manchester. The aims are to add high-level synthesis capabilities to these tools and to extend the tools such that a wider range of (higher speed) micro-architectures can be generated. Another branch of research takes a conventional synchronous circuit as the starting point, and then adds some form of handshake-based flow-control. One approach keeps the global clock and implements discrete-time asynchronous operation. Another approach substitutes the clocked registers by asynchronous handshake-registers, thus creating truly continuous-time asynchronous circuits that operate without a clock. The perspective here is that the substitution/conversion is done as the final step in an otherwise conventional synchronous design flow.

Abstract: A scan chain circuit causes a plurality of flip-flops to function as shift registers during execution of a scan test and can execute a scan shift that serially transfers test pattern data for the scan test. A clock gating circuit controls output of a pulse of a clock signal supplied to the scan chain circuit in accordance with a clock gating signal, whereas disables the clock gating signal based on a logic of a scan enable signal authorizing the scan shift. A first clock gating circuit included in the clock gating circuit disables the clock gating signal during the scan shift based on the logic of the scan enable signal and also inverts the clock signal and outputs a result of inverting.

Abstract: Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and means for delaying a synchronizing clock signal supplied to at least one of the plurality of combinational logic groups based upon a period of the synchronizing clock signal and the propagation time of the at least one combinational logic group. In another embodiment, a method includes delaying a clock signal to produce a delayed clock signal and communicating the clock signal and the delayed clock signal to separate groups of the combinational logic circuit during a clock cycle that results in a reduction in power consumption by the combinational logic circuit.

Abstract: A shift register has a plurality of shift register units coupled in series. Each shift register includes a pull-up circuit, an input circuit, a pull-down circuit, a compensation circuit, an input end, an output end and a node. Each shift register unit receives an input voltage at the input end and provides an output voltage at the output end. The input circuit transmits the input voltage to the node based on a first clock signal. The pull-up circuit provides the output voltage based on a second clock signal and the voltage level of the node. The pull-down circuit selectively connects the node with the output end according to a third clock signal. The compensation circuit is coupled to the input circuit, the pull-down circuit and the node for maintaining the voltage level of the node based on the second and third clock signals.

Abstract: This paper presents a new adiabatic logic which drives two-phase clocking. The proposed adiabatic logic (2PC2AL) uses two trapezoidal-wave pulses and resembles behavior of static CMOS. The structure of 2PC2AL can be directly derived from static CMOS logic circuits. We also propose a trapezoidal-wave generator compatible to 2PC2AL. The proposed clock generator is based on the switched capacitor circuit. From the simulation results, we show that the energy consumption of the proposed circuit is lower than that of CMOS logic circuits in the range of from 1 to 100 MHz, and the 4-bit multipliers also are about 30n50% lower.

Abstract: A clock receiver includes a capacitive coupling circuit for filtering out direct-current voltages from a differential clock signal. In this way, the capacitive coupling circuit rejects common-mode noise in the differential clock signal. The clock receiver also includes a bias circuit for establishing a bias voltage in the differential clock signal and a differential amplifier for amplifying the differential clock signal. Further, the differential amplifier generate a feedback differential clock signal and provides the feedback differential clock signal to the bias circuit for further rejecting common-mode noise in the differential clock signal. The feedback differential clock signal functions as a negative feedback signal for rejecting common-mode noise in the differential clock signal and as a positive feedback signal for amplifying the differential clock signal. In some embodiments, the clock receiver includes a capacitive coupling circuit with a cut-off frequency above the frequency of the differential clock signal.

Abstract: The synthesis and simplification of digital circuits are performed in the well known two level logic switching algebra. By increasing the representation domain to B levels it is possible to design Multiple-Valued Logic (MV Logic)digital circuits. This work proposes an algebra based on a universal set of gates which carry out operators to allow synthesis and simplification of MV Logic digital circuits. This paper addresses: the generated algebra; the algebraic form of the function to be synthesized based on the canonical form of the Sum Of Extended Product terms; the duality; and circuit simplification procedures. Combinatorial and sequential circuits are synthesized to demonstrate the correctness of the algebra. The proposed algebra allows designing any MV Logic digital circuit taking advantage of the knowledge coming from the binary circuits by extending it to the MV Logic digital circuit synthesis.

Abstract: A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.

Abstract: A flip-flop circuit includes: a first latch circuit that receives input of a data signal and a rise delay clock signal, raises a signal of a first node according to the fall of the rise delay clock signal, and lowers the signal of the first node according to the rise of the rise delay clock signal; a second latch circuit that receives input of the signal of the first node and the clock signal and lowers a signal of a second node at timing when the clock signal falls; a third latch circuit that receives input of the signal of the second node and the clock signal and generates an output signal for maintaining the data signal; and a pull-down circuit that pulls down the signal of the first node with the rise delay clock signal.

Abstract: Apparatus and methods detect missing clock edges. An improved phase frequency detector (PFD) can be used in, for example, a phase locked loop (PLL) or a delay locked loop (DLL). Conventional PFDs can miss clock edges. Disclosed is a missing clock edge detection circuit that reliably detects these missing clock edges to correctly activate switches of a charge pump of the PLL or DLL. Embodiments exhibit relatively little of the characteristic polarity reversal of conventional PLL or DLL circuits, which then enables embodiments to operate faster and acquire phase lock quicker than conventional circuits. Such techniques are useful in clock synthesis, clock recovery, and the like. The invention can further include an optional circuit that detects when the missing clock edge detection circuit may have inaccurately determined (false positive) that a clock edge had been missed, to override the corrective action by the missing clock edge detection circuit.

Abstract: In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

Abstract: The present invention relates to an all-digital clock data recovery (CDR) which is implemented by a digital filter and a digitally controlled oscillator. The CDR of the present invention comprises a phase detector producing a digital sequence of data and a digital sequence of edge by sampling the serial data stream with a clock, a de-serializer transforming the digital sequences of data and edge into n-bit bus, a digitally controlled oscillator (DCO) implemented by a multi-stage chain of inverters having a variable resistance switching matrix wherein the resistance of each element of the variable resistance switching matrix is varied in such a way that the supply current being fed to each inverter is controlled in pursuant to a digital control code, and thereby producing a clock whose oscillation frequency is updated and fed to the phase detector, a digital synthesis control logic circuit generating a thermometer-code-type digital control code out of the n-bit data and n-bit edge from the de-serializer wherein the thermometer-code-type digital control code is fed to the DCO, and a 2-bit direct forward path directly controlling the frequency of the clock being produced by the DCO with an operating speed which is faster than the digital synthesis control logic circuit by n times.

Abstract: There is a growing concern about timing errors resulting from design marginalities and the effects of circuit aging on speed-paths in logic circuits. This paper presents a low overhead solution for masking timing errors on speed-paths in logic circuits. Error masking at the outputs of a logic circuit is achieved by synthesis of a non-intrusive error-masking circuit that has at least 20% timing slack over the original logic circuit. The error-masking circuit can also be used to collect runtime information when the speed-paths are exercised to (i) predict the onset of wearout and (ii) assist in in-system silicon debug. Simulation results for several benchmark circuits and modules from the OpenSPARC T1 processor are presented to illustrate the effectiveness of the proposed solution. 100% masking of timing errors on all speed-paths within 10% of the critical path delay is achieved for all circuits with an average area (power) overhead of 16% (18%).

Abstract: Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).

Abstract: Effective timing and power characterization flows are described for asynchronous circuits. Verification can be provided for both relative-timing constraints as well as performance (e.g., throughput) targets using commercially-standard STA tools. Fully-automated scripts are developed that verify all relative timing assumptions (e.g., isochronic forks) as well as the gate-level performance of any circuit designed with these templates. Library characterization can be utilized and asynchronous logic cells not found in standard-cell libraries, such as dual-rail domino logic and dynamic C-elements with staticizers, can be characterized in terms of both their timing and power. These values are a function of both input slew and output load and are preferably captured in an industry standard format, such as the Liberty format, before being compatible with commercial STA tools. Using a characterized library, timing correctness and performance of an asynchronous circuit can be analyzed either through back-annotated simulations or preferably static analysis.

Abstract: Asynchronous circuits are well known for their benefits in terms of dynamic power savings because asynchronous logic does not switch when inactive. Nevertheless, in deep-submicron technologies, leakage currents have become an increasing issue, and thus, asynchronous circuits need to focus on static-power-consumption reduction. In this paper, we propose an innovative way to detect incoming asynchronous activity. Associated to an automatic power regulation, it efficiently reduces the supply voltage and, thus, both energy per operation and leakage currents. The proposed technique has been applied to an asynchronous network-on-chip node and successfully implemented in an ST Microelectronics CMOS 65-nm technology.