Abstract: This invention relates to a digital/analog converter circuit, a level shift circuit, a shift register containing this level shift circuit, a sampling latch circuit and a latch circuit as well as a liquid crystal display device mounted with these respective circuits, wherein a drive circuit integrated with the LCD device containing the digital/analog converter circuit has polysilicon thin film transistors arrayed in a matrix on the substrate as switching devices for the pixels, a level shift circuit in the shift register has a basic structure of CMOS latch cells and is utilized in each level shift of the clock signal at each transfer stage, a sampling latch circuit with a basic structure of CMOS latch cells has a level shift function, and these respective circuits may be incorporated into a single scanning type structural circuit with the drive circuit-integrated liquid crystal display device to provide an LCD panel with an extremely narrow picture frame, stable level shift operation, stable sampling & latch operation in a circuit structure having an extremely small number of components, low power consumption and a small surface area.

Abstract: A delay locked loop (DLL) circuit includes a first delay control unit configured to generate a first delay control signal in response to a first phase detection signal to control a delay amount of a first delay line and to output a first delay amount information signal, a second delay control unit configured to generate a second delay control signal in response to a second phase detection signal to control a delay amount of a second delay line and to output a second delay amount information signal, and to control the delay amount of the second delay line again in response to the first delay control signal and a half cycle information signal, a half cycle detecting unit configured to receive the first delay amount information signal and the second delay amount information signal to extract half cycle information of a reference clock signal, thereby generating the half cycle information signal, and a duty cycle correcting unit configured to combine an output clock signal from the first delay line and an output clock signal from the second delay line, thereby outputting a duty ratio correction clock signal.

Abstract: This paper presents an ultra-low power circuit design methodology which combines the Multi-Threshold CMOS (MTCMOS) technique with quasi delay-insensitive (QDI) asynchronous logic, in order to solve the three major problems of synchronous MTCMOS circuits: (1) Sleep signal generation, (2) storage element data loss during sleep mode, and (3) sleep transistor sizing. In contrast to most power reduction methods that result in area overhead, the QDI asynchronous MTCMOS circuits are usually smaller than their original versions. Moreover, QDI circuits utilize handshaking protocols instead of clocks for circuit control, resulting in flexible timing requirements, which yields increased circuit robustness and allows for extreme supply voltage scaling to subthreshold region for further power reduction, without requiring any circuit modifications. This QDI asynchronous MTCMOS methodology is used to design a 4-stage pipelined 8-bit x 8-bit unsigned multiplier, which is then compared against the original QDI design (i.e., without incorporating MTCMOS) and its synchronous version. All designs use the IBM 8RF-DM 0.13 μm process. Results show 150x and 1.8x leakage power and active energy reductions on average in the QDI asynchronous MTCMOS design compared to the original QDI version, respectively.

Abstract: An inductive coupling reader includes a passive interface circuit for modulating the impedance of an antenna circuit and extracting from the antenna circuit a data signal and a RF clock signal, and circuitry for coupling the reader to a removable security module The reader includes an emulation circuit for opening a RF transmission channel with another reader, a non-removable electrical link linking the emulation circuit to the passive interface circuit, by which the data signal and the RF clock signal are supplied to the emulation circuit, and a data bus clocked by a bus clock signal having a frequency inferior to the frequency of the RF clock signal, for linking the emulation circuit to the removable security module The reader has low electrical consumption

Abstract: Provided are a method and apparatus for controlling a read latency of a high-speed DRAM. A memory device may include a delay measurement unit, a delay locked loop, a latency counter and a data output buffer. The delay measurement unit measures a delay time between when an external clock signal is input and when read data is output to generate measurement signals and generates a first internal clock signal delayed from the external clock signal. The delay locked loop (DLL) receives the first internal clock signal and generates a second internal clock signal synchronized with the external clock signal. The latency counter generates a latency signal from an external read command signal in response to the measurement signals, and the data output buffer outputs the read data in response to the latency signal and the second internal clock signal.

Abstract: Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR gates, and buffer gates. If the logic gates at the same level are in different types, which have different timing behaviors, the control of clock skew becomes difficult. Based on that observation, in this paper, we present a novel clock tree design style, called type-matching clock tree, to ensure that the logic gates at the same level are in the same type. We prove that any clock control logic can always be transformed to our type-matching clock tree. Then, based on the idea of type-matching clock tree, we propose a zero skew gated clock tree synthesis algorithm. Compared with the industry- strength gated clock tree synthesis, experimental data show that our approach can significantly reduce the clock skew in every process corner with a small penalty on the clock tree area and the clock tree power consumption.

Abstract: This paper presents a reliability analysis algorithm that can be integrated in the design flow of logic circuits. Based on a four state representation of signal probabilities, and the propagation of this probabilities along the cells of a circuit, the signal reliability of the circuit can be directly obtained. The use of signal probabilities rises the well known problem of signals correlation, and we present some relaxing conditions that allow tradeoffs between accuracy and execution time of the algorithm. The main advantages of the proposed methodology are its simplicity and straightforward application, allowing an easy integration with design tools.

Abstract: The invention includes a system and method of modifying a setting of a NAND flash memory device using serial peripheral interface (SPI) communication from a master to the NAND flash memory device. One embodiment generally includes sending an enable signal to a first memory circuit input, sending a clock signal to a second memory circuit input, sending a command signal synchronized to the clock signal to a third memory circuit input, sending a memory register address signal synchronized to the clock signal to the third memory circuit input, and sending a setting signal synchronized to the clock signal to the third memory circuit input.

Abstract: A re-configurable test circuit for use in an automated test equipment includes a test circuit, a test processor and a programmable logic device. The pin electronics circuit is configured to interface the re-configurable test circuit with a DUT. The test processor includes a timing circuit configured to provide one or more adjustable-timing signals having adjustable timing. The programmable logic device is configured to implement a state machine, a state sequence of which depends on one or more input signals received from the pin electronics circuit, to provide an output signal, which depends on a current or previous state of the state machine, to the pin electronics circuit in response to the signal(s) received from the pin electronics circuit. The test processor is coupled to the programmable logic device to provide at least one of the adjustable-timing signal(s) to the programmable logic device to define timing of the programmable logic device.

Abstract: Digital circuits operating in the sub-threshold regime are able to perform minimum energy operation at a given delay. In the sub-threshold regime circuit delay, hence the leakage energy consumption depends on the supply voltage exponentially. By reducing the idle time of the circuit both the supply voltage that realizes minimum energy operation and the energy consumption can be reduced. This paper presents an in-depth comparison of synchronous and asynchronous techniques in the sub-threshold operating regime for their energy efficiency. First, transistor level accurate high level sub-threshold energy consumption model is developed for both techniques. Afterwards, using the model, energy consumption reduction due to the asynchronous operation is investigated analytically. Different architectural improvements such as pipelining and parallelism are considered. The model has also been applied to the benchmark circuits for comparing real world energy consumption values. From our analysis and simulations we have found out that asynchronous operation in the sub- threshold regime significantly lowers the supply voltage value that realizes the minimum energy operation and operating the digital circuits at a lower supply voltage value result in lower energy operation. Asynchronous operation resulted in energy consumption savings of up to 51% on the ISCAS85 benchmark circuits synthesized in a digital CMOS 0.18 m process.

Abstract: Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions under which the transition of a register may be safely blocked can either be explicitly specified by the designer or detected automatically. We introduce a new method for automatically synthesizing these conditions in a way that minimizes netlist perturbation and is both timing- and physical-aware. Our automatic method is also scalable, utilizing simulation and satisfiability tests and necessitating no symbolic representation. On a set of benchmarks, our technique successfully reduces the dynamic clock power by 14.5% on average. Furthermore, we demonstrate how to apply a straightforward logic simplification to utilize resulting don't cares and reduce the logic by 7.0% on average.

Abstract: A key challenge in using timing-robust asynchronous circuit styles is the lack of automated optimization techniques. In this paper, technology mapping and cell merger algorithms for asynchronous threshold networks are introduced. The cell merger problem is a restricted form of technology mapping where only adjacent cells are merged. The two algorithms can each target either delay or area, or a combined delay-area cost function. Experiments were performed on substantial industrial design examples (DES and GCD circuits) that had already been optimized by an existing commercial asynchronous synthesis tool flow. Average delay improvements of 31.6% for basic technology mapping and 29.6% for basic cell merger were obtained. Average area improvements of 9.5% for basic technology mapping and 8.5% for basic cell merger were also obtained. Additional experiments were performed on the largest MCNC combinational benchmarks with similar results. Finally, targeting a hybrid cost function, area minimization under specified hard timing constraints, a further area reduction of up to 10.7% on average in technology mapping was recovered without compromising the overall system performance. The new algorithms are the first systematic and general mapping approach for asynchronous threshold networks, targeting delay or area, which preserve the timing-robustness properties of the initial unoptimized circuits.

Abstract: A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.

Abstract: To detect problematic circuit behaviour, such as potential hazards and deadlocks, in a reasonable amount of time a technique is required which would avoid exhaustive exploration of the state space of the system. Many of the existing methods rely on symbolic traversal of the state space, with the use of binary decision diagrams (BDDs) and associated software packages. This paper presents an alternative approach of using a special type of Petri nets to represent circuits. An algorithm for automatic conversion of a circuit netlist into a behaviourally equivalent Petri net is proposed. Once the circuit Petri net is constructed and composed with the provided environment specification, the presence and reachability of troublesome states is verified by using methods based on finite prefixes of Petri net unfoldings. The shortest trace leading to a deadlock or a hazard in the circuit Petri net is mapped back onto the gate-level representation of the circuit, thus assisting a designer in solving the problem. The method has been automated and compared against previously existing circuit verification tools.

Abstract: Disclosed is a clock generation circuit for generating a clock-out signal that has a fixed latency with respect to a clock-input signal. When multiple such clock generation circuits are utilized to feed clock signals to different digital logic circuits within an integrated circuit structure, differences in delay time, referred to as skew, are minimized. An embodiment of the clock generation circuit incorporates a waveform generator and a timing-improved deskewer. The waveform generator is clocked by a clock-in signal. The deskewer comprises a flip-flop, a level-sensitive latch, and a multiplexer. The flip-flop and latch are connected in parallel and each receives waveform signals from the waveform generator as well as the clock-in signal in order to generate output signals. The multiplexer gates the flip-flop and latch output signals with the clock-in signal in order to generate the clock-out signal. A testable deskewer for edge-sensitive multiplexer scan designs is also disclosed.

Abstract: Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.

Abstract: A system is provided with clock skew measurement and correction technology. A first circuit or memory controller 4 includes measuring circuits to measure relative timing or phase offsets of multiple clock signals of a second circuit or memory 6. One measuring circuit is configured for incremental changing of the phase of a transmitted test data sequence to measure and correct timing of a memory receiver circuit's quadrature clocks based on results of a data comparison of transmitted and received test data. Another measuring circuit is configured to scan a received test data sequence for data transitions to measure and correct timing of a memory transmitter circuit ' s quadrature clocks based on spacing or timing between detected transitions. Individual memory clock generators 30 are controlled with adjustable delay circuits 47 for changing phase of different clock signals of the memory to set the clock signals based on the measurements of the controller.

Abstract: A method of designing an asynchronous integrated circuit is provided. A global clock network of a synchronous circuit is replaced with a plurality of handshaking circuits. Data validity is encoded into a communication path between a first pipeline stage and a second pipeline stage of the synchronous circuit. A control logic for the first pipeline stage is implemented using a template that contains characterization information for timing to generate an asynchronous circuit design.

Abstract: Techniques are disclosed for clustering circuit paths in an electronic design automation process for use in improving the timing characteristics of the overall circuit design. Circuit paths included in the cluster may be subjected to placing and routing as a group to relocate instances of circuit components included in the clustered circuit paths to thereby improve the overall circuit design timing.

Abstract: The implementation of interconnect is becoming a significant challenge in modern integrated circuit (IC) design. Both synchronous and asynchronous strategies have been suggested to manage this problem. Creating a low skew clock tree for synchronous inter-block pipeline stages is a significant challenge. Asynchronous interconnect does not require a global clock, and therefore, it has a potential advantage in terms of design effort. This paper presents an asynchronous interconnect design that can be implemented using a standard application-specific IC flow. This design is considered across a range of IC interconnect scenarios. The results demonstrate that there is a region of the design space where the implementation provides an advantage over a synchronous interconnect by removing the need for clocked inter-block pipeline stages, while maintaining high throughput. Further results demonstrate a computer-aided design tool enhancement that would significantly increase this space. A detailed comparison of power, area, and latency of the two strategies is also provided for a range of IC scenarios.

Abstract: In a semiconductor device capable of radio communication, a stable clock signal is generated even if a reference clock signal for generating a clock signal has varied frequencies in each cycle. A clock signal generation circuit includes an edge detection circuit that detects an edge of an input signal and generates a synchronization signal, a reference clock signal generation circuit that generates a clock signal which functions as reference, a counter circuit that counts the number of edges of rise of the reference clock signal in accordance with the synchronization signal, a duty ratio selection circuit that selects a duty ratio of a clock signal from a count value, and a frequency division circuit that generates the clock signal having the selected duty ratio.

Abstract: Boosting operation of a charge pump is performed at a fixed period irrespective of the state of a load. A regulator for controlling a charge pump includes: a frequency dividing circuit generating a frequency-divided clock having a period that is twice that of a boost clock; a voltage dividing circuit generating a plurality of divided voltages having voltage values that differ from one another; a comparator circuit comparing each of the divided voltages and a reference voltage and outputting a plurality of comparison-result signals; a selection signal generating circuit reading in logic of each of the comparison-result signals in synch with an edge of the frequency-divided clock and outputting selection signals; a duty converting circuit outputting a plurality of clocks having different ON duties; a selector selecting any one of the plurality of clocks or “H”-level logic as a PWM signal based upon the selection signals; and a gate circuit taking the logical AND between the frequency-divided clock and the PWM signal and generating control signals for controlling series-parallel switching.

Abstract: Spacecraft routinely experience extreme environmental conditions, including cryogenic (as low as -230degC) and elevated temperatures (as high as +130degC). Presently, the temperature of the spacecraft electronics is regulated to its safe operating temperature. The need for temperature regulation on current spacecrafts imposes significant constraints on spacecraft design and also limits performance. This paper details efforts to develop a DC motor drive operational in extreme ambient temperatures (-230 to +130degC). The circuitry of this motor drive is to be based on mature, commercially available technologies and a custom silicon germanium (SiGe) low power asynchronous 8051-pin-compatible microprocessor ASIC. In this paper, the authors present results of passive and active commercial component testing carried out to date, a discussion of the developed automated asynchronous logic design flow, and a discussion of ultra-wide temperature range NULL Convention Logic (NCLtrade) IC design work accomplished to date. Developments made during this research project will allow for a more rapid and more reliable circuit design of ultra-wide range or cryogenic electronics, particularly NCL circuits and power electronic circuits.

Abstract: A system for driving multiple charge pumps in a single unit is disclosed. The charge pump system includes a set of multiple charge pumps arranged in parallel. The charge pumps are connected to a clock signal generator, which generates clock signals that direct the charging of the charge pumps and are offset in time from one another. The clock signals may be generated such that rising edges of the clock signals are separated by a specified time interval. The clock signals may be generated by a ring oscillator using signals provided by stages of the oscillator to generate the multiple signals. The clock signals may also be generated by providing a single input clock signal to a multi-phase generator, which outputs a set of clock signals having different phases based on the input clock signal. The system may also be configured to generate the offset clock signals using other methods, such as using a programmed microcontroller or using spread spectrum techniques.

Abstract: Asynchronous circuits are well-known for their benefits in terms of dynamic power savings, because asynchronous logic does not switch when inactive. Nevertheless, in deep-submicron technologies, leakage currents have become an increasing issue, and thus asynchronous circuits need to focus on static power consumption reduction. In this paper, we propose an innovative way to detect incoming asynchronous activity. Associated to an automatic power regulation, it efficiently reduces the supply voltage and thus both energy per op. and leakage currents. The proposed technique has been applied to an asynchronous network-on-chip node, and successfully implemented in a STM 65 nm technology.

Abstract: With the continuous shrinking of devices dimensions in microelectronic circuits, it is becoming extremely desirable to integrate analog circuitry together with complex digital logic blocks. The noise generated by the digital parts in a mixed-signal integrated circuit is inevitably transmitted to the analog parts, through the power supply networks and through the common silicon substrate. Therefore, in the past years a lot of attention has been drawn to alternative digital logic circuit styles that are more friendly than classical CMOS in a mixed-signal environment. MOS Current-Mode Logic (MCML) is a differential logic circuit style that provides high-speed operation together with low generation of supply noise, and is thus a natural candidate for implementing digital blocks in mixed-signal circuits. In this work, MOS Current-Mode Logic circuits are studied, with a focus on the implementation of standard-cell based digital circuits. To this aim, a design methodology is proposed to build efficient MCML standard-cell libraries, and a complete top-down design flow allowing the construction of complex digital circuits with differential standard-cells is proposed. The results of implementing a digital encoder block for analog-to-digital applications are presented.

Abstract: Embodiments of a power-regulator circuit having two operating modes are described. This power-regulator circuit includes control logic that is configured to select a given operating mode based on a load condition of the power-regulator circuit. During a first operating mode, the control logic provides a first signal that operates the power-regulator circuit as a linear regulator. Moreover, during a second operating mode, the control logic provides a second signal and a third signal that operate the power-regulator circuit as a switch-mode regulator.

Abstract: The memory system comprises: a semiconductor memory that includes an internal circuit, which operates according to a first power supply voltage, and a memory input/output circuit, which is coupled to the internal circuit and operates according to a second power supply voltage; a first control unit that includes a control input/output circuit, which is coupled to the memory input/output circuit and operates according to the second power supply voltage; a voltage generating unit that generates the second power supply voltage and changes the second power supply voltage according to a voltage adjustment signal; a clock generating unit that generates the clock signal and changes the frequency of the clock signal according to a clock adjustment signal; and a second control unit that generates the voltage adjustment signal and the clock adjustment signal according to an access state of the semiconductor memory by the first control unit.

Abstract: A reset signal generation circuit for generating a reset signal synchronously or asynchronously to a clock signal in accordance with an operation state. An operation detection circuit detects operation of a CPU and generates an operation detection signal. A signal control circuit generates a first reset signal synchronously or asynchronously to an internal clock signal based on the operation detection signal and a system reset signal. The first reset signal is provided to synchronous circuits including the CPU.