Abstract: A synthesis method that utilizes timing constraints to generate timed asynchronous circuits is presented. By unfolding the cyclic graph specification of an asynchronous circuit into an infinite acyclic graph, it is possible to use efficient algorithms to analyze the given timing constraints. A sufficient condition for the removal of redundancy in the specification is derived. Because of this condition, it is only necessary to analyze a finite subgraph of the infinite acyclic graph for derivation of a correct implementation. A systematic synthesis procedure that further optimizes the implementation based on the timing constraints is applied to the reduced specification. It is shown that the resulting timed implementation can be significantly reduced in complexity from its speed-independent counterpart while remaining hazard-free under the given timing constraints. >

Abstract: In this paper, we present a CAD tool for the synthesis of asynchronous control circuits using basic gates such as AND gates and OR gates. The synthesized circuits are speed-independent; that is, they work correctly regardless of individual gate delays. We present synthesis results for a variety of specifications taken from industry and previously published examples. We compare our speed-independent circuits with those non-speedindependent circuits synthesized using the algorithms described in [I], in which delay elements are added to remove circuit hazardr. These synthesis results show that our circuits are on average approximately 25% faster with an area penalty of only IS%. This work demonstrates that direct synthesis of gate-level speed-independent circuits is not only feasible, but also produces robust and relatively efJrcient circuits compared to those synthesized with timing constraints.

Abstract: The authors study the problem of delay fault modeling and test generation for any random logic sequential circuit. The proposed test generation method, based on transition and hazard states of signals, is applicable to any sequential circuit of either non-scan, scan or scan-hold type of design. Three fault models based on different initial state assumptions during the propagation of the fault effect to a primary output are proposed and analyzed using the proposed delay fault test generation method. A novel thirteen-value algebra is considered to simplify the analysis of robust and nonrobust tests during fault simulation of path delay faults. >

Abstract: Continuous advances in VLSI technology have made it possible to implement a system on a chip. One consequence of this is that the system will use a homogeneous technology for interconnections, gates, and synchronizers. Another consequence is that the system size and operation speed increase, which leads to increased problems with timing and synchronization. System and delay models necessary for the study of time performances of synchronous and asynchronous systems are developed. Clock skew is recognized as a key factor for the performance of synchronous systems. A mode of clocking that reduces the clock skew substantially is proposed and examined. Time penalty introduced by synchronizers is recognized as a key factor for the performance of asynchronous systems. This parameter is expressed in terms of system parameters. Different techniques and recommendations concerning performance improvement of synchronous and asynchronous systems are discussed. >

Abstract: CMOS chips are becoming increasingly important in computer circuitry. They have been widely used during the past decade, and they will continue to grow in popularity in those application areas that demand high performance. Challenging the prevailing opinion that circuit simulation can reveal all problems in CMOS circuits, Masakazu Shoji maintains that simulation cannot completely remove the often costly errors that occur in circuit design. To address the failure modes of these circuits more fully, he presents a new approach to CMOS circuit design based on his systematizing of circuit design error and his unique theory of CMOS digital circuit operation. In analyzing CMOS digital circuits, the author focuses not on effects originating from the characteristics of the device (MOSFET) but on those arising from their connection. This emphasis allows him to formulate a powerful but ultimately simple theory explaining the effects of connectivity by using a concept of the states of the circuits, called microstates. Shoji introduces microstate sequence diagrams that describe the state changes (or the circuit connectivity changes), and he uses his microstate theory to analyze many of the conventional CMOS digital circuits. These analyses are practically all in closed-form, and they provide easy physical interpretation of the circuit's working mechanisms, the parametric dependence of performance, and the circuit's failure modes. Originally published in 1992. The Princeton Legacy Library uses the latest print-on-demand technology to again make available previously out-of-print books from the distinguished backlist of Princeton University Press. These editions preserve the original texts of these important books while presenting them in durable paperback and hardcover editions. The goal of the Princeton Legacy Library is to vastly increase access to the rich scholarly heritage found in the thousands of books published by Princeton University Press since its founding in 1905.

Abstract: The power consumption of an electrical device can be optimised by altering the clock frequency of circuits (MCU, 1-3) in the device which are controlled by a clock signal. The state and need for processing power of the circuits (MCU, 1-3) or blocks (21-23) in the circuits (2) is supervised, and the clock frequency of the circuit (MCU, 1-3) or block (21-23) in the device is changed according to the need for processing power. The appropriate clock frequency is selected from one of a plurality of clock signals (clk(1) . . . clk(n)), input to a selection circuit which is then coupled to the output of the selection circuit for use as the clock for the circuit.

Abstract: The authors evaluate their proposed asynchronous state-machine synthesis method, which uses locally synthesized clocks, on two realistic examples: a DRAM controller and a small computer systems interface controller. These circuits are designed to satisfy existing interface specifications, and are substantially larger than interfaces that have been created by competing methods, such as signal transition graph synthesis. The performance of the resulting implementations is at least as good as that of comparable synchronous implementations. >

Abstract: The authors propose a novel framework to solve the state assignment problem arising from the signal transition graph (STG) representation of an asynchronous circuit They first solve the STG state assignment problem by minimizing the number of states in the corresponding finite-state machine (FSM) and by using a critical race-free state assignment technique State signal transitions may be added to the original STG A lower bound on the number of signals necessary to implement the STG is given The technique significantly increases the applicability of STGs for specifying asynchronous circuits >

Abstract: The problem of bridging fault simulation under the conventional voltage testing environment is considered. A method to provide electrical-level simulation accuracy, without paying the associated performance penalties, is proposed. A three-level simulation model is used, balancing the tradeoffs among gate-level, switch-level, and electrical-level simulation. Large memory overheads are avoided by localizing the fault, and by performing electrical-level simulation only in the area around the fault. This approach is sufficiently flexible to model feedback faults, BiCMOS circuits, stuck-open faults, and any fault that can be described with a circuit netlist. Tests were run on several ISCAS combinational and sequential benchmark circuits, using realistic cells and transistor parameters; results show that accurate simulations can be performed in reasonable time.<>

Abstract: A method and apparatus for testing input and output parameters for high speed integrated circuit devices An integrated circuit tester generates a receive clock and a transmit clock using a pair of pre-selected output pins The integrated circuit tester adjusts the phase relation between the transmit clock and the receive clock Special circuitry within the device under test compares input and output data to detect errors

Abstract: A clock distribution circuit with multiple clock drivers distributing a clock signal on multiple signal paths has active de-skewing logic circuitry for equalizing the total clock delay to the different clock recipient circuits in a system The de-skewing logic uses a return path parallel to the outward signal path to sense the propagation delay and includes a phase comparator with inputs receiving the return signal and a reference signal for comparison of their phase Voltage-controlled delay elements, responsive to a control voltage provided by a charge pump controlled by the phase comparator, adds or removes equal amounts of delay to the outward and return signal paths until the return signal phase matches that of the reference signal Each clock driver may have its own de-skewing circuitry or may share a common reference signal In one embodiment the de-skewing circuitry for each driver time-shares a common phase comparator and charge pump, using sample-and-hold circuits to store the control voltages obtained by the comparisons Input receivers on the return paths may have selectable input buffers to take into account the different buffer delays of different logic family types of the clock recipients

Abstract: Clocking systems and methods of the present invention use two or more different clock signals for respective groups or stages of self-timed dynamic (or mousetrap) logic gates Each clock signal defines a precharging time interval and an evaluation time interval for its respective group or stage of self-timed dynamic logic gates Using the two or more different clock signals, pipelining of the groups or stages of the self-timed dynamic logic gates can be performed

Abstract: In classical switching theory, asynchronous sequential circuits are operated in the fundamental mode. In this mode, a circuit is started in a stable state, and then the inputs are changed to cause a transition to another stable state. The inputs are not allowed to change again until the entire circuit has stabilized. In contrast to this, delay-insensitive circuits-the correctness of which is insensitive to delays in their components and wires-use the input-output mode. In this case, it is assumed that inputs may change again, in response to an output change, even before the entire circuit has stabilized. It is shown that such commonly used behaviors as those of the set-reset latch and Muller's C-ELEMENT do not have delay-insensitive realizations, if gates are used as the basic components. It is proved that no nontrivial sequential behavior with one binary input possesses a delay-insensitive realization using gates only. The proof makes use of the equivalence between ternary simulation and the general-multiple-winner model of circuit behavior. >

Abstract: In a multichip integrated circuit module (4), the number of effective input/output pins (3, 5, respectively) is increased by using techniques of TDM (time division multiplexing). A first chip (1) has at least one output shift register (9). A second chip (1) has at least one input shift register (7). Interconnection wires (19) couple the output shift registers (9) and the input shift registers (7). Means (15) are provided for loading data in parallel to the output shift registers (9). Means (17) are provided for sequentially shifting data through the output shift registers (9) over the interconnections (19) and into the shift input registers (7). Embodiments of the invention are described for use in conjunction with bi-directional pins (25), tri-state output drivers (21), and asynchronous logic (18).

Abstract: Field-programmable gate arrays are frequently used to implement system interfaces and glue logic. However, there has been little attention given to the special problems of these types of circuits in FPGA architectures. In this paper we describe Montage, a Triptych-based FPGA designed for implementing asynchronous logic and interfacing separately-clocked synchronous circuits. Asynchronous circuits have different requirements than synchronous circuits, which make standard FPGAs unusable for asynchronous applications. At the same time, many asynchronous design methodologies allow components with greatly different performance to be substituted for one another, making a design environment which migrates between FPGA, MPGA, and semi-custom implementations very attractive. Similar problems also exist for interfacing separately-clocked synchronous circuits. We discuss these problems, and demonstrate how the Montage FPGA satisfies the demands of these classes of circuits.

Abstract: We describe a new automatic synthesis tool (3D) for designing asynchronous controllers from burst-mode specifications, a class of specifications allowing multiple input change fundamental mode operation. We present an algorithm for constructing a three-dimensional next-state table, a heuristic for encoding states, and a procedure for generating necessary constraints for exact logic minimization. We demonstrate the effectiveness of the 3D implementation and the synthesis procedure on numerous designs including a large realistic example (Asynchronous Data Transfer Protocol of the SCSI Bus Controller). We estimate the latency (input to output delay) and the cycle time (time required for the circuit to stabilize after the excitation) for all benchmark designs using a 0.8pm CMOS standard cell library.

Abstract: The transfer gate between the master section and the slave section in a flip-flop circuit includes a circuit for reducing the sensitivity to slow clock edges and clock skew. This is accomplished by prolonging the transfer time for data from the master to the salve section of the flip-flop circuit.

Abstract: A timing control circuit to be used for a phase locked loop (PLL) wherein, a plurality of delay circuit elements capable of controlling the delay connected in series are used as a signal delay circuit, delay values of all the delay circuit elements can be changed at the same time with the delay control signals of the respective delay circuit elements being commonly connected, and the delay control signal is controlled so as to select the desired delay with the combination of a selecting circuit, a bi-directional shift register circuit, a phase detecting circuit, a shift control circuit, a delay control circuit so as to realize the wide range of timing control, thereby to provide a function of adjusting the delay of a signal delay circuit for effecting a timing control operation.

Abstract: Clock signals (68-71) synthesized by a first phase-locked loop circuit (60) are monitored by a second phase-locked loop circuit (87). The second phase-locked loop circuit (87) additionally provides clock signal synthesis redundancy and monitors the functional status of the first, signal synthesizing phase-locked loop circuit (60). One (71) or more of the primary clock signals (68-71) are supplied to an input selector (85) which selects and divides, if necessary, one of its input clock signals (33,34,71) and supplies a predetermined frequency signal (86) to the second phase-locked loop circuit (87), the output signal (89) of which is divided (90) to produce a redundant set of clock signals (91-94), one (94) of which is used as a comparison frequency in the second phase-locked loop circuit (87). If the second phase-locked loop circuit (87) detects an out-of-lock (72') condition it supplies a signal (88) to a microcontroller (56) that controls the selection of input clock signals (33,34,71,94) to input selectors (85,55) of the second and first phase-locked loop circuits (87,60) and the selection of clock signal sets (68-71,91-94) by an output selector (75). The circuitry may be used in a telephone communication system (Fig. 1).

Abstract: The authors propose a novel framework to solve the state assignment problem arising from the signal transition graph (STG) representation of an asynchronous circuit. They first solve the STG state assignment problem by minimizing the number of states in the corresponding finite-state machine (FSM) and by using a critical race-free state assignment technique. State signal transitions may be added to the original STG. A lower bound on the number of signals necessary to implement the STG is given. The technique significantly increases the applicability of STGs for specifying asynchronous circuits.

Abstract: A digital-analog driver circuit for a plural-phase brushless D.C. motor includes a logic circuit responsive to commutation control signals for generating commutation gating signals, a digital function generation circuit responsive to a commutation signal supplied by the logic circuit and further responsive to a high frequency clocking signal, for generating a pulse width modulated digital function signal having a base period of the high frequency clocking signal and a timed interval synchronized to the commutation signal and for supplying the digital function signal to the logic circuit, the logic circuit including a function signal inversion circuit for generating an inverted digital function signal, and having a gating circuit for selectively putting out the digital function signal and the inverted digital function signal in synchronism with the commutation signal, plural digital to analog converters each for converting the digital function signal and the inverted digital function signal into an analog phase driving signal, and plural phase transistor drivers each being responsive to a said analog phase driving signal, for applying a driving current to a phase winding of the brushless D.C. motor.

Abstract: An integrated circuit has a signal path including a first circuit that introduces a propagation delay that decreases with circuit conditions and process speed in series with a second circuit that introduces a propagation delay that increases with circuit conditions and process speed. The circuit conditions and process speed are sensed and the duration of the propagation delay of the second circuit varied such that the total propagation delay remains within a predetermined range over circuit condition and process speed variations. In another embodiment of the invention, a current source develops a bias current to control the duration of the propagation delay of the second circuit. In yet another embodiment of the invention the current source is a current mirror.

Abstract: A balanced tree clock distribution network for an integrated circuit including a branching clock line of layered metal in which each branch of the clock line has equal resistance, apparatus for shielding the clock line on both sides in the same layer of material of the integrated circuit, and apparatus for providing jumpers for crossing the clock line at right angles in a different layer of material of the integrated circuit which jumpers appear at the same preselected distances along each branch of the clock line.

Abstract: Retiming is an effective technique to optimize the performance of synchronous sequential circuits. This paper proposes a method to improve the effectiveness of retiming by transforming the sequential circuit. Bottlenecks which prevent retiming to achieve a desired clock period are identified. Conditions to eliminate the retiming bottlenecks are derived. These conditions are satisfied by a process of identifying sub-circuits and satisfying a set of timing constraints on the sub-circuits. The transformed circuit, which satisfies the timing constraints, can be retimed to achieve the desired clock period. If the original circuit has its initial state specified, our method always generates the final circuit with an equivalentinitial state. Experimental results on a variety of sequential benchmark circuits demonstrate significant performance improvement.

Abstract: A new method is developed for generating tests for path delay faults in synchronous sequential circuits using any available sequential circuit test generation program. All paths through the combinational logic are searched and two potential faults for each path, corresponding to the propagation of rising and falling signals at the source of the path, are considered. To generate a test sequence for a path delay fault, we augment the netlist model of the circuit under test with a logic block such that the testing for a certain single stuck type fault in this block is equivalent to the testing of the path delay fault. The added logic consists of a pair of flip-flops and a few combinational gates that are driven by the signals feeding the gates on the path. A stuck-at-1 fault in this logic is activated and its effect is latched into the destination flip-flop of the path only when all signals along the path are set in the states required for the delay test. The fault efSect is then propagated to a primary output. The test sequence for the stuck fault, thus performs all three functions, namely, initialization, path activation and fault propagation, required for the testing of the delay fault. We use a sequential circuit test generator to obtain a test sequence for this stuck type of fault. A hazard avoidance procedure to produce robust tests, although not fully implemented in our prototype test generator, is given. Experimental results on sequential benchmark circuits show the practicality of this method for general nonscan as well as for scan and scanlhold type of circuits.

Abstract: In the design of high speed digital VLSI circuits, it is preferable that the clock net be routed on the metal layer with the smallest RC delay. This strategy not only avoids the difficulties of having different electrical parameters on different layers, but also eliminates the delay and attenuation of the clock signal through vias. The clock phase-delay is also decreased. An algorithm, based on max-min optimization, to construct a planar clock tree which can be embedded on a single metal layer is presented. The clock tree achieves equal path lengths, i.e., the lengths of the paths from the clock source to each clock terminal are exactly the same. In addition, the path length from the source to clock terminals is minimized. Some examples including industrial benchmarks have been tested, and the results are promising. >

Abstract: The design of complex, high performance systems requires automation of the design process. At the outset of automation, the focus of synthesis was to obtain small realizations that could be implemented as integrated circuits. However, with improvements in fabrication technology, the area of a design is of secondary importance and the performance of the circuit is the primary criterion that the designer wishes to maximize. Circuit performance is affected by various decisions taken during different phases of the design process. This thesis provides an understanding of the factors that affect the delay of logic circuits. Logic circuits are represented as an interconnection of functional units and registers. To improve the speed of an initial implementation, the designer may apply different types of optimizations. Using a set of bounded-input functions, functional units can be implemented by circuit structures that have small depth by repeated application of local transformation on the circuit. This phase is referred to as technology-independent optimization. Reduction in circuit depth usually leads to smaller delay. However, circuit speed also depends on the choice of gates used to implement the function. Gates differ in their delay characteristics. To utilize this flexibility technology-dependent optimizations are required. The paradigm of applying local transformations is extended to exploit the delay characteristics of gates during optimization. In circuits that contain registers, the freedom in positioning registers allows for further synchronous optimizations.