Abstract: A method of partial scan design is presented in which the selection of scan flip-flops is aimed at breaking up the cyclic structure of the circuit. Experimental data are given to show that the test generation complexity may grow exponentially with the length of the cycles in the circuit. This complexity grows only linearly with the sequential depth. Graph-theoretic algorithms are presented to select a minimal set of flip-flops for eliminating cycles and reducing the sequential depth. Tests for the resulting circuit are generated by a sequential logic test generator. An independent control of the scan clock allows insertion of scan sequences within the vector sequence produced by the test generator. An independent control of the scan clock allows insertion of scan sequences within the vector sequences produced by the test generator. 98% fault coverage is obtained for a 5000-gate circuit by scanning just 5% of the flip-flops. >

Abstract: The invention is a method of designing an integrated circuit in which the steps of designing the circuit are optimized by a formal hierarchy. This method, called Timing Driven Placement, of designing an integrated circuit avoids detailed optimization which consumes enormous computational resources. It organizes physical and logical characteristics of the design so that those characteristics can be optimized with respect to the physical design of the circuit. The characteristics are optimized and the resulting circuit to location assignment is placed and wired with a conventional automated process. The method optimizes the global placement into precincts of logic segments of the circuit design with respect to the segment placement effect on circuit timing and wireability. The method then migrates individual circuits within particular segments to other segments to improve both the individual segment and overall circuit timing and wireability. Finally, the method transfers circuit assignment to logic segment and logic segment assignment to physical location information to a conventional process for final detailed circuit placement and wiring.

Abstract: Synthesis support for the design of asynchronous circuits is crucial. The synthesis method proposed starts from a graph-theoretic specification called a signal transition graph (STG). This work deals with the theoretical foundations of a method to transform a given STG into an STG that satisfies the original timing behavior and that in addition obeys the unique state coding requirement. It is shown that in general, many valid solutions to this problem are possible. The authors find a transformed STG that can be realized in a circuit with optimized speed and area. >

Abstract: Delay analysis in logic simulation is enhanced by providing, in a simulation model of a logic circuit, a timing delay tag on each circuit path connecting the output (30;10) of a first (BLK1;BLK4) with the input (A0,D01) of the second circuit element (BLK4;BLK3). Each circuit leg is given a delay value and a clock phase tag providing information about how the delay value is clocked. The clock phase tags (T0,...,T3) correspond to respective phases of a multi-phase circuit clock and relate the delay values to particular clock phases. The phase tag also indicates whether the signal on the data path is triggered by the rising (R) or falling edge of the specified clock phase. At circuit nodes, clock phase tags are concatenated. Thus, if a clocked circuit element responds to an input signal which is a composite of several upstream output signals, the concatenated clock phase tags and delay values can be analyzed to determine if a timing adjustment is required. The information further supports the automatic adjustment of delay value, if needed.

Abstract: This paper shows how high-level synthesis bridges the gap between behavioral specifications and hardware structure by automatically generating a circuit description from a netlist. The resulting description can be used for other design automation tools, such as logic synthesis and layout. As opposed to logic synthesis, which optimizes only combinational logic, high-level synthesis deals with memory elements, the interconnection structures, (such as buses and multiplexers), and the sequential aspects of a design. The steps in the process of synthesizing synchronous digital hardware are explained. They consist of compilation, high-level transformations, scheduling, and allocation. Design representation is discussed, and problems remaining to be solved are indicated. >

Abstract: Signal delay, chip area, and power dissipation are conflicting criteria for designing high-performance VLSI MOS circuits. Global optimization of transistor sizes in digital CMOS logic circuits with the design tool multiobjective gate-level optimization (MOGLO) is described. Analytical models for the design objectives are presented, and algorithms are discussed. Different techniques were combined to solve the circuit optimization problem with low computational costs. Precise gate-level delay models guarantee meaningful results, especially for high-speed logic circuits. >

Abstract: A description is given of: (1) a finite-state model for asynchronous systems in which the time delays between the scheduling and occurrence of the events that cause state changes are constrained to fall between fixed numerical upper and lower time bounds; (2) a branching-time temporal logic suitable for describing the temporal and logical properties of asynchronous systems, for which the structures of (1) are the natural models; and (3) a functional verification system for asynchronous circuits which generates, from a Boolean circuit with general feedback and specified min/max rise and fall times for the gates, a finite-state structure as in (1), and then exhaustively checks a formal specification of that circuit in the language (2) against that finite-state model. >

Abstract: The Act-2 family of CMOS field-programmable gate arrays (FPGAs) uses an electrically programmable antifuse and novel architectural and circuit features to obtain higher logic densities while increasing speed and routability. Improvements include: two new logic modules, novel I/O and clock driver circuitry, and more flexible and faster routing paths. New addressing circuitry shortens programming time and speeds complete testing for shorts, opens, and stuck-at faults. Fully automatic placement and complete routing are retrained. Special software tools used for architectural exploration and layout generation are discussed. >

Abstract: The needs for multi-gigabits/second digital electronics in advanced lightwave systems have motivated R & D for the next generation of high speed bipolar technology. The speed of the digital circuit may be estimated from the propagation delay of the logic gate. We discuss physics of the delay and show that it is fundamentally limited by the time needed for turning on (off) a transistor and by the time for charging (discharging) of capacitances in the circuit. We present a large-signal theory based on a charge-control model for the calculation of these limits. The results obtained for emitter coupled logic and current mode logic are used to analyze current technologies of silicon bipolar and GaAs HBTs.

Abstract: A novel method is described for verifying the equivalence between a combinational circuit and its specification, when both are given in a modular (e.g., factored) form. It is based on the notion of cross-controllability and cross-observability relations that exist between the internal logic values across a cut of the joint composition of the circuit and the specification. It is proven that even after abstracting input and other internal variables the relations are sufficient to verify the equivalence. The abstraction allows reduction of the size of the relation, thus permitting the verification of much larger circuits. A report is presented on the verification of an 8*8 parallel multiplier using at most 527 BDD (binary decision diagram) cells of 21 variables. Extensions to sequential circuits are also discussed. >

Abstract: The disclosure concerns the manufacture of integrated circuits and, more precisely, that of integrated circuits containing a signal processor To be able to make a purely internal clock in an integrated circuit, wherein this clock does not require any external adjusting elements connected to terminals of the circuit, the clock is designed to include an internal oscillator, the frequency of which is adjustable by a register, it being possible for the register to be loaded by the processor The frequency of the oscillator may be adjusted to compensate for the uncertainty over the natural frequency of the oscillator (which is subject to technological fluctuations) It may also be used to adjust the frequency as a function of an application or of the environment of the circuit The contents of the register may come from a non-volatile memory containing individual data on the circuit

Abstract: A logic compiler wherein verification of a generated circuit model is performed automatically by comparing the operation of the circuit model with that of a corresponding mathematical behavior model. A novel user interface and circuit model generation means enables the user to obtain, in real time, performance specifications on the circuit selected by the user as well as incurring other benefits.

Abstract: In designing an integrated circuit having a logic circuit area and a clock supplying circuit, the layout of the clock supplying circuit can be designed before the completion of the layout designing of the logic circuit area. Clock buffers and wires that are component elements of the clock supplying circuit are arranged in a peripheral region of the logic circuit area. This arrangement enables the layout designing of the clock supplying circuit to be done with no influence of the layout designing of the logic circuit area.

Abstract: A circuit for generating a plurality of timing signals includes a plurality of cascade-connected delay cells, each having an input coupled to an output of another, and a plurality of latches. Set inputs of various latches are coupled to outputs of various delay cells to determine times of occurrence of leading edges of various timing pulses. Reset inputs of the various latches are coupled to outputs of various delay cells to determine times of occurrence of trailing edges of various timing pulses. The circuit includes a phase detector having a first input coupled to receive a clock signal and a second input coupled to an output of one of the delay cells to receive a signal indicative of propagation of a logic state through a first group of the delay cells, to produce an adjustment signal indicative of whether the phase of the indicator signal is ahead of or behind the phase of the clock signal. Each of the delay cells increases or decreases propagation time through that delay cell in response to the adjustment signal, so as to cause a time required for the logic state to propagate through all of the delay cells to be equal to a period of the clock signal.

Abstract: An output buffer circuit for an integrated circuit for outputting an amplified signal from a sense amplifier which senses information stored in a memory cell of random access memory for improving operation of the integrated circuit is disclosed The output buffer circuit comprises NAND gates ND1, ND2 operatively connected to the output of the sense amplifier to receive first and second output signals S1, S2, and operatively connected to receive a control signal φ1 from the integrated circuit which operates the memory cell to read A MOSFET Q1 and a MOSFET Q2 are utilized with both MOSFETs turning on or off depending upon the signals applied to their gates An output loading capacitor CL is operatively connected to the junction P4 and to the ground A logic combination means 10 connected to junctions P1, P2 performs a logical combination of the signal applied through the junction P4 and the control signal φ1 applied to the input points of the logic combination means An output means 20 is connected between the logic combination means 10 and the junction P4, thereby controlling the output level of the output buffer circuit to a middle level depending upon the signal from the logic combination means

Abstract: An approach to the design of multilevel, multi-output combinational logic circuits in which all path delay faults are detectable by robust tests is proposed. Inadequacies of previous approaches for synthesis for testability of path delay faults are discussed. A necessary and sufficient condition for the existence of a hazard-free robust test for a path is stated. Violation of this condition is adopted as the criterion for identifying the paths, in a given circuit, which are not testable by hazard-free robust tests. Transformation methods to render these paths testable are proposed. >

Abstract: The device comprises a control circuit (2) integrating a power transistor (4) controlling the electrical power supply of a load (3), detectors (7, 8, 9) and a logic circuit (10) connected to a computer (1) by two lines (I/0) and (SEL). According to the invention, the computer selectively and successively controls, by specific combinations of logic signals applied on the lines (I/0) and (SEL), several logic sub-circuits for the detection and identification of functional faults in the power supply circuit of the load (permanent control, short-circuit, open circuit), the circuit (2) in return imposing on the line (I/0) logic levels representative of the presence or absence of faults, during time intervals in which the computer is configured to read these levels. Application to the diagnosis of the functional status of electro-valves forming part of a wheel anti-­locking device on a vehicle.

Abstract: Novel quaternary logic circuits, designed in 2- mu m CMOS technology, are presented. These include threshold detector circuits with an improved output voltage swing and a simple binary-to-quaternary encoder circuit. Based on these, the literal circuits, the quaternary-to-binary decoder, and the quaternary register are derived. A novel scheme for improving the power-delay product of pseudo-NMOS circuits is developed. Simulations for an inverter indicate a 66% improvement over a conventional pseudo-NMOS circuit. Noise-margin and tolerance estimations are made for the threshold detectors. To demonstrate the utility of these circuits, a quaternary sequential/storage logic array (QSLA), based on the Allen-Givone algebra has been designed and fabricated. The prototype chip occupies an area of 4.84 mm/sup 2/, is timed with a 2.2-MHz clock, and consumes 93 mW of power. >

Abstract: A PLL lock indicator circuit for indicating when a phase-lock-loop circuit is in lock includes a gate circuit coupled to the phase/frequency detector of the phase-lock-loop circuit for providing an output logic signal that is responsive to output logic signals from the phase/frequency detector being in a predetermined state. A counter circuit is enabled by the output logic signal of the gate circuit for providing an output logic signal when the counter circuit has reached a predetermined count. A latch circuit is responsive to the output logic signal of the counter circuit for providing a lock signal at an output terminal of the circuit, the lock signal being indicative of when the PLL circuit is in phase lock.

Abstract: A digital phase lock loop decoder for decoding Manchester encoded data includes a controllable delay line (52) which provides a PLL CLOCK signal, which is delayed in respective further delay lines (58,62) and a compensating delay (66), to provide three phased clock signals (CLK1,CLK2,CLK3) defining a window for sampling the incoming data signal (RD). The sampled signals are applied to phase compare logic (86) which provides control signals for a counter (96), in dependence on the samples in the current and previous windows. The 7-bit counter output is fed back to control the phase of the controllable delay line (52) such that the central phased clock signal (CLK2) coincides with the mid-bit data transition. When data is not being received a delay correction section (34) continuously updates a compensating value which compensates for delay variations and is stored in a latch (142) for use during data reception.

Abstract: Although the theory of asynchronous circuits (fates back to the early 1950s, considerable progress has been made in this area in the past five years This paper constitutes the first part of a two-part survey of the recent advances in this field Part I of the survey presents a unified and concise overview of those aspects of the theory that (leaf with the behavior of circuits under the assumption that delays in the circuit components and wires are unbounded The historical development of the subject is presented, and some shortcomings of the earlier approaches are discussed Ternary simulation is related to the binary analysis methods; the ternary approach is then used to correct the flaws in the earlier work The question of realizability of sequential behaviors is then considered It is shown that the class of realizable behaviors is rather severely restricted by the unbounded-delay assumption and that the use of bounded-delay models is more realistic Part 11 of the survey will deal with bounded-delay models, MOS circuits, classical and delay-insensitive design methods, and complexity issues

Abstract: An electronic clock has a single Josephson junction connected in parallel to a resonant circuit, which is a delay line with a matching resistance at the input end to provide series termination. The opposite end of the delay line is an open end to reflect pulses, and the pulse transit time on the line determines the clock rate. A zero crossing detector is provided to initiate the clock operation when an input signal rises above a given threshold, and a reset circuit is included to turn off the clock when the input signal falls below this threshold. A flip-flop circuit allows the clock to be turned on by alternate initiating signal pulses. A modification includes a pulse rejuvenating circuit at the end of the delay line to offset pulse degradation. All of the circuits are fabricated with Josephson junction elements, and the zero crossing detector, reset circuit, flip-flop circuit and pulse rejuvenator circuits include dc-SQUID's. The clock is capable of operation at frequencies up to 100 GHz and can sample input single frequencies as high as 15 GHz.

Abstract: A method of testing integrated circuits at high operating speeds is provided which is applicable to sequential logic circuits such as ASICs. A general purpose ASIC tester applies test vectors to the integrated circuit under test. The logic input signals are held unchanged and a series of high speed clock signals (a clock burst) are applied to the clock terminals of the integrated circuit. These clock signals are provided at the speed at which it is desired to test the integrated circuit. Then the output terminals are observed to determined if the device is in the expected state (as determined by simulation) after the clock burst. The process is repeated until no further output terminals change state, and then the device may be reinitialized and another series of state changes initiated. Thus every path in the circuit may be tested at high speed by a conventional low speed tester.

Abstract: A two-phase clock generator generates a nonoverlapping two-phase clock from a unipolar input clock by utilizing gate delays in first and second signal paths. The output of each signal path is fed over a cross-coupled feedback path back to a logic gate in the respective other signal path. Each logic gate is a floating inverter having a first supply terminal connected to a supply voltage, and having a second supply terminal that is the feed point for the respective feedback signal from the output of the other signal path.

Abstract: A simple model is presented for estimating the delay of a multi-level combinational logic description prior to a technology-dependent mapping phase. The model proposes that delay through a node varies logarithmically with both the complexity and the fanout of the node's logic equation. This is a consequence of the observation that in high performance circuits, both the fan-in and fan-out of cells are bounded by small numbers. Model parameters are derived for three different CMOS ASIC (application specific integrated circuit) libraries, and the authors show how the predicted delays compare with the actual delays for three different industrial designs in each library. This model can serve as a proxy for delay during technology-independent logic optimization, much as literal counts serve as proxies for area. >

Abstract: A programmable logic device includes AND-plane and OR-plane. The AND-plane includes first input signal lines (B1, B1, B2, B2) having input signals transmitted, product term lines (A1-A4), a first precharge circuit (3b), a clock generator (15) for generating a first clock signal, and a dummy circuit (7b) having dummy output lines which have the precharge finished in response to the first clock signal and the discharge made at a speed less than the slowest discharge speed of the product term lines. The OR-plane includes second input signal lines (AB1-AB4), sum term lines (01-04), dummy input lines (ADB1, ADB2) to be charged at a speed less than the lowest charge speed of the second input signal lines, and second precharge circuit (5b). The programmable logic device further includes a second clock generator (8c; 8d; 8e) for generating a second clock signal and circuitry (16) for generating a third clock signal in response to the external clock, and circuitry (L1-L4) for latching the signal potential on the sum term lines so as to derive the output signals. The respective two sum lines are arranged in a pair, and one discharge signal line (CD1-CD4) is provided to the pair.

Abstract: A transient-error free interpolating decimator utilizes only two comb filters. The decimator has an integrator circuit, which receives a digitized signal at a first clock rate, and a differentiator circuit. The differentiator includes first and second comb filters for down converting the digital signal at the first clock rate to a second clock rate, and for providing sample points at first and second outputs; the differentiator circuit and the integrator circuit comprise a decimation filter. A delay circuit provides coarse sampling phase adjustments by delaying the second clock rate by a predetermined number of first-clock cycles. A counter generates the second clock rate and provides coarse sampling phase adjustments by adding or deleting cycles of the first clock to or form the second clock. A multiplexer circuit swaps the two outputs when necessary to prevent transient errors generated in the differentiators from being observed. An interpolator circuit makes fine sampling phase adjustments by interpolation to provide an output that is transient-error free. The interpolator circuit includes a bypass circuit for bypassing the first output of the multiplexer circuit for preventing transient errors from being observed.

Abstract: A noncontact IC card comprises a data transmit-receive circuit for transmitting and receiving data without contact, a detection circuit for detecting a trigger signal in a signal received by the data transmit-receive circuit, a data processing circuit connected to the data transmit-receive circuit for processing the data, a clock generating circuit for supplying a clock signal to the data processing circuit, an actuating circuit for actuating the clock generating circuit in response to the detection of the trigger signal by the detection circuit, and a battery for supplying electric power to each of the above circuits.

Abstract: The operation of analog circuit blocks is simulated on a digital computer by a computer program in which each analog circuit block is represented by a procedure call including details of input signal name(s) and value(s), output signal name(s) and value(s), the operating parameters for the block and the sampling instant for the evaluation of the or each output signal value. The interconnections between blocks are represented by the use of the same signal names. Each sampling instant indicates when the value of an output signal will have changed by a predetermined amount since the previous sampling instant. A common sampling time is used for the circuit and is selected as the earliest of the sampling instants of the circuit blocks. The simulation can include digital circuit blocks represented by an event-driven or a levelised compiled code model, with analog/digital conversion to handle the interconnections between analog and digital circuit blocks. A feedback connection around part of the analogue circuit is handled by progressive adjustment of the feedback input signal value while other input signal values are held constant.