Abstract: An asynchronous logic cell and a two- or three dimensional array formed of such cells. Each cell comprises a number of exclusive-OR gates, Muller C-elements and programmable switches. The logic cell is reprogrammable and may even be reprogrammed dynamically, such as to perform recursive operations or simply to make use of hardware which is temporarily idle. Programming is accomplished by setting the states of the switches in each cell. A user-friendly programming environment facilitates the programming of the switches. The array can be used to implement any circuit capable of being modelled as a broad class of Petri Nets. Configurations for (i.e., programs for setting cell switches to create) circuit blocks such as adders, multiplexers, buffer stacks, and so forth, may be stored in a library for future reference. With an adequate library, custom hardware can be designed by simply mapping stored blocks onto chips and connecting them together. Further, because the array is regular and switch settings can produce logical wires, crossovers, connections and routings running both "horizontally" and "vertically", it is in general possible to "wire around" defective elements. If a large wafer contains defective cells, those cells can simply be avoided and bypassed, with the remainder of the wafer remaining useful.

Abstract: A one-chip semiconductor device comprises a semi-conductor substrate with power supply terminals and data terminals. Formed on the substrate are a clock generating circuit for generating a clock signal when a power supply voltage is applied to it through the power supply terminals, a data processing circuit which is driven by the clock signal to process the data supplied to it through the data terminals, a first voltage detecting circuit for producing a stop signal when it detects that the power supply voltage falls below a first reference voltage, and a second voltage detecting circuit for producing a reset signal when it detects that the power supply voltage falls below a second reference voltage. The stop signal stops the clock generating circuit, whereby the data processing circuit stops and remains in the same condition as is driven by the clock signal. The reset signal initializes the data processing circuit. The first reference voltage is the lowest value which enables the data processing circuit to operate stably. The second reference voltage is the lowest value which enables the data processing circuit to remain in the same condition as is driven by the clock signal.

Abstract: A signal delay device comprises a CMOS gate circuit (12, 14) having an input terminal (13) to which a binary input signal to be delayed is applied, an output terminal (15) from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means (16,18) is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit. The signal delay device using the CMOS gate circuit is applied to various circuits including an analog signal delay circuit, a jitter absorption circuit and a fixed head type magnetic tape reproducing device.

Abstract: A circuit and method for generating a substantially smooth clock for clocking asynchronous data to a user device. Incoming asynchronous data is stored in an elastic buffer such as a first-in first-out memory. Periodically, an output identifiable bit is read into the memory and a multibit digital signal corresponding to the number of output clock pulses for it to be read out is determined. This signal, which corresponds to the occupancy of the first-in first-out memory, is used to generate an analog voltage which controls a voltage controlled oscillator that provides the substantially smooth clock for reading data out of the first-in first-out memory. The control loop causes the long term rate of the smooth clock to be substantially equal to the incoming asynchronous data rate.

Abstract: A phase synchronization circuit for controlling a graphic display device in a teletext receiving system. The phase synchronization circuit includes a delay circuit, adapted to delay in sequence clock signals which are to be phase-synchronized with a reference signal and to produce in sequence delayed clock signals, and a selection circuit, including set/reset circuits and gates, each gate receiving the output of the set/reset circuits and of the delayed clock signals. Among the delay clock signals, the signal that has the nearest edge timing to the edge of external signals is selected. The phase synchronization circuit has a short pull-in time and high-speed synchronization, is suitable for circuit integration, and offers improved reliability.

Abstract: The sequential behavior of CMOS logic circuits in the presence of stuck-open faults requires that an initialization input followed by a test input be applied to detect such a fault. However, a test set based on the assumption that delays through all gates and interconnections are zero, can be invalidated in the presence of arbitrary delays in the circuit. In this paper, we will present a necessary and sufficient condition for the existence of a test set, which cannot be invalidated under arbitrary delays, for an AND-OR or OR-AND CMOS realization for any given function. We will also introduce a Hybrid CMOS realization which, for any given function, is guaranteed to have a valid test set under arbitrary delays.

Abstract: A digital signal delay circuit which delays a plurality of digital input signals by a use of a single delay device group and a plurality of delay sections is disclosed. The delay device group generates a plurality of different phase clock signals. Each of the delay sections includes selection means for selecting one of the clock signals from the delay device group and latch means for latching the digital input signal in response to the output signal from the selection means. The output signal from the latch means is the delayed input signal, and a delay time is controlled by the selection means. The delay device group is used in common for the plurality of delay sections, so that the digital signal delay circuit is simple and inexpensive in construction.

Abstract: In the disclosed digital circuit, a digital direct sequence modulation signal is converted to a suppressed clock pulse-duration modulation signal to thereby suppress the clock feature in the frequency spectra of a spread spectrum transmission system. The disclosed digital circuit includes a parallel output shift register for converting the direct sequence modulation signal to a corresponding series of four-bit digital words. The digital words supplied by the shift register are loaded into a four-bit synchronous binary counter circuit. The counter circuit counts upwardly from the value of the digital word and supplies a carry pulse to a logic circuit which, in turn, produces an output pulse, the duration of which is representative of value of the digital word supplied by the shift register. The pulse-duration modulation signal supplied by the logic circuit is modulo-2 added with a signal having one-half the clock rate of the information embedded in the direct sequence modulation signal to supply the suppressed clock pulse-duration modulation signal.

Abstract: A self-checking detector for detecting faults in a multiple redundant clock system includes a majority voter circuit for receiving the clock signals from the redundant clock circuits and for providing a voted output, a comparison circuit for comparing each of the clock signals with the voted output, and failure signal producing circuits responsive to the outputs from the comparison circuit for producing a first failure signal upon a clock failure being detected and for producing a second failure signal upon a failure of the majority voter being detected. The detector further includes power-up reset circuitry for inhibiting its operation during a power-up interval, and a reset circuit enabling either automatic or manual reset of the detector for verification of the detected fault.

Abstract: Thorough delay testing of a combinational logic circuit is accomplished by changing only one input at a time (a single transition), and checking the output at a predetermined short time later, and arrangements are disclosed for systematically applying to the inputs of a combinational logic circuit all possible single transitions of the binary input signals. One economical test circuit uses a conventional binary counter and an associated ring counter to generate the test signals, in addition to input switching circuits or multiplexers for steering data to the logic to be tested and control circuitry to control the test process.

Abstract: Introduction to digital systems principles of switching algebra design of combinational circuits digital circuit components implementation of combinational circuits sequential circuits design of synchronous sequential circuits design of asynchronous circuits design of iterative arrays digital circuit testing and design for testability system design and design automation Appendices: ANSI/IEEE Logic symbols answers to all tutorial problems

Abstract: A multi-functional fuzzy logic circuit comprises at least one input circuit provided for at least one input current for producing at least one output current of the same value in the same direction as the input current and at least one output current of the same value in the reverse direction, and a plurality of fuzzy logic circuits for executing different fuzzy logic operations, each of the fuzzy logic circuits having as its input at least one of said output currents produced by said input circuit.

Abstract: A CMOS boost word-line clock and decoder-driver circuit which can be used for CMOS DRAM's with substrate bias in addition to VDD supply. A boost word-line clock circuit including simple CMOS inverters is used for the word-line boost and the possible voltage overshoot, which usually occurs because of capacitor two-way boost, can be completely eliminated. Also, the circuit can be triggered by a single clock. A high performance decoder circuit is provided in combination with the aforesaid CMOS boost word-line clock circuit, such decoder using NMOS pass-gate in the decoder driver and providing fast word-line boosting. The timing between the decoder and the word-line clock activation is not crucial.

Abstract: A CMOS D-type flip-flop circuit stage for avoiding the possibilty of feedthrough includes a non-overlapping clock generator section having a true clock output and a complement clock output. The flip-flop circuit includes a master section formed of a first transfer gate, a first regenerative transistor and a first inverter gate. The flip-flop circuit further includes a slave section formed of a second transfer gate, a second regenerative transistor and a second inverter gate. The clock generator provides a two-phase non-overlapping clock for clocking both the master and slave sections so as to prevent inadvertent racethrough of data input to successive stages.

Abstract: A power on/off reset generator (5) for monitoring a power supply (10) for a logic system powered from the monitored power supply. A precision-voltage sensor (20) produces a control signal for a time delay circuit (30) when the power supply rises above a preselected threshold voltage (E T ). A delay signal is generated which maintains an active-LOW control signal to the logic system and causes a Schmitt trigger circuit (40) to produce a HIGH control signal to the logic system at the end of the delay signal.

Abstract: A converter or running-key for generator producing pseudo-random sequences under the supervision of a secret or confidential key or code is substantially formed by a combination device containing a memory circuit and a feedback circuit. Periodic digital sequences are summed in an adder circuit, and the thus obtained composite digital sequence is separated in a divider circuit. A part of this composite digital sequence is used as a digital feedback sequence which is fed to an input of the same adder circuit through the feedback circuit comprising an auxiliary digital memory device or storage and an auxiliary logic circuit. In this manner, the desired memory and feedback is achieved which results in more complicated or complex pseudo-random sequences. In an advantageous exemplary embodiment, a substitution block is inserted as the auxiliary digital memory device or storage. This substitution block can be implemented by a commercially available read-and-write memory (RAM).

Abstract: An asynchronous signal synchronizing circuit for sampling and external asynchronous signal in a quarter of the period of a clock. A first latch circuit latches asynchronous input signal in accordance with a first clock, and a second latch circuit latches the output of the first latch circuit in accordance with a second clock having a phase shift 180° out of phase with the first clock. A third latch circuit latches the output signal of the second latch signal in accordance with a clock signal that represents the inverse of the first clock. A fourth latch circuit latches the output signal of the third latch circuit under the control of a clock that corresponds to the inverse of the second clock. The asynchronous input signal is sampled at the tailing edge of the first clock signal and validated by the tailing edge of the second clock signal. The synchronization of the asynchronous signal can thus be performed in a quarter of a clock cycle.

Abstract: A data delay/memory circuit includes clock-controlled data latch circuits formed with cascade-connected clocked inverters. The data delay/memory circuit also includes a clock generator for supplying the clocked inverters with clock signals. These clock signals have individual clocking phases and are sequentially generated such that the clocking phase for a final stage of the data latch circuits is ahead of that for an initial stage thereof.

Abstract: An input buffer circuit, especially well-suited for use as a TTL-TO-CMOS interface circuit, has a differential transistor pair at the input for stabilizing the circuit switching point relative to logic level voltage transitions occurring at the input. A preferred embodiment of the circuit has a first switching device in the input stage for decreasing the circuit response time to a first (e.g., high-to-low) logic level transition, and a second switching device for decreasing the response time to a second (e.g., low-to-high) logic level transition. Output buffers, in the form of inverters, may also be provided.

Abstract: An integrated circuit having a built-in self test design, the integrated circuit including a combinatorial logic circuit, a first register coupled to an output of the combinatorial logic circuit and a feedback path via which output signals from the first register are fed back to an input of the combinatorial logic circuit. A multiplexer is provided between the first register and the feedback path, and there is also provided a second register responsive to a signal which is originated to initiate a test function for feeding test signals via the multiplexer and the feedback path to the input of the combinatorial logic circuit.

Abstract: The switching network logic (SNL) design method is introduced. It is a systematic approach to the design of MOS circuits based on the switching network concept. The double-rail SNL and single-rail SNL are discussed in which the single-rail SNL makes efficient use of the negation property of MOS circuits. The SNL circuits have better performances than those of MOS circuits designed with NAND-NOR-gate or negative-gate approaches. Moreover, the SNL circuit is guaranteed to be minimal for SC and SP functions.

Abstract: A digital circuit which ascertains the middle of a digital pulse by first determining its total length through digital logic means in combination with a digital signal delay means, and uses this information to operate a state machine (or sequencer), which will assume that data clocks occur at the time of the last received valid data pulse until new logic "1" data is received, and at this time can be resynchronized or phase-locked if there is a time discrepancy between recently received data and the status of the state machine.

Abstract: A dynamic, multistage CMOS logic circuit is driven with a single source of clock pulses. The clock pulses operate odd-numbered stages. A static delay circuit provides clock pulses to even-numbered stages. The dynamic and static circuits are designed according to a discipline that guarantees the elimination of race conditions in the dynamic circuit despite the presence of uncontrollable variations in pullup and pulldown delays in the fabrication process.

Abstract: An up/down counter device includes a D-type flip-flop circuit for producing a count signal of the 0th bit in synchronism with a clock signal, and 1st to n-th flip-flop circuits for producing count signals of the 1st to the n-th bits in synchronism with a clock signal. The first logic circuit is connected between the output of the D-type flip-flop circuit and the JK terminals of the first flip-flop circuit. The first stage logic circuit includes a first logic circuit section supplied with an up/down mode signal and the output signal of the D-type flip-flop circuit, and a second logic circuit connected in series with with the first logic circuit. Each of the 2nd to the n-th stage logic circuits includes a first logic circuit which is connected between the output terminal of the prestage flip-flop circuit and the JK terminals of the post stage flip-flop circuit, and a second logic circuit section connected to the first logic circuit. The output of the first logic circuit section of each of the first to the n-th logic circuits is connected to the input of the first logic circuit section of the post stage logic circuit.

Abstract: SEU testing of both combinatorial and sequential CML of identical technologies with Cf252 and Am241 heavy ion sources revealed agreement in the numbers of device disturbances in both categories of logic. The data confirms that terminal latch upset is primarily due to flip-flop toggling rather than by data path combinatorial logic disturbances.

Abstract: A number of logic forms and clocking schemes for cMOS integrated circuits are in common use. The most common logic form consists of two networks of transistors, the gates of which are connected to the input variables. An n-channel network defines the boolean condition under which the output is connected to ground (logic zero). A p-channel network defines the complementary condition under which the output is connected to a logical one. Since in many cMOS processes the output of a single pass transistor cannot be guaranteed to exceed the logic threshold of a typical inverter, pass transistor networks are either forbidden or a complementary transmission gate employing both p and n-channel devices is used. Clocking schemes for cMOS presently offer tradeoffs over a wide range in the risk vs efficiency space. In one scheme, a single phase clock and its complement are distributed, and used to control either transmission gates or transistors controlling power to the p and n-channel switching networks. Proper operation in either case requires that the logic delay of the stage exceeds the skew between the two clock lines. In a much safer approach, a two-phase clock is used, both the clock and its complement being distributed for each phase. In this case risk is eliminated at the expense of doubling the clock wiring. Yet another form is popular in gate-level designs. A single clock is distributed, and locally inverted at masterslave storage elements. Risk in this case is eliminated at the expense of a minimum storage element employing ten or more transistors. In this paper we describe a logic form that retains much of the simplicity, elegance, and compactness of the familiar 2-phase nMOS form, with the added advantage of fully static operation. Formal semantics for circuits implemented in this form are easily derived without detailed circuit or switch-level simulation.

Abstract: A highly reliable, fail-safe circuit for a control system wherein a controlled device will always receive a control signal derived from a main control circuit when the main control circuit operates normally even if a back-up control circuit backing up at least one function of the main control circuit which is a minimum requirement for an operation of the controlled device fails or wherein a controlled device will receive a control signal derived from the back-up control circuit when the main control circuit fails. Replacement of the control signal from the main control circuit with a back-up control signal from the back-up circuit is carried out only when the back-up circuit outputs a particular signal at or near a predetermined frequency or alternatively when the back-up circuit outputs a plurality of parallel logical signals in a predetermined combination.