Abstract: A solid state delay circuit responsive to power turn-on for delaying the start-up and operation of a system until power has stabilized is disclosed. The delay circuit is particularly useful where the delay and program initialization system is used with or includes computers and computer operated equipment.

Abstract: The bucket-brigade circuit offers a means of implementing a clock-controlled analog delay line in monolithic form. Operating in the sampled-data domain, it combines some of the advantages of both analog and digital circuits and appears to have a strong application potential in analog signal processing systems. In this paper, the analog operation of bucket-brigade circuits is described with respect to such practical operating considerations as bandwidth, dynamic range, linearity, power dissipation, baseband, signal recovery, a clock waveform noise. Experimental results from p-channel MOSFET and n-channel JFET brigades are presented.

Abstract: An interface circuit arrangement between a random noise generator circuit and an output digital logic integrated circuit. The interface circuit includes a digital logic integrated circuit which has impedance levels and voltage levels compatible with that of the output digital logic integrated circuit and which is connected within a closed loop including a differential amplifier which biases the interface digital logic integrated circuit into a symmetrical amplification region substantially midway within its linear range of operation thereby removing a threshold selectivity which otherwise reduces the randomness of the output of the random noise generator.

Abstract: A theoretical and experimental investigation of adaptive logic elements suitable for use as an output interface for digital stochastic computers is presented. An adaptive digital element using a binary rate multiplier is demonstrated to provide a significant improvement in accuracy without reduction in bandwidth characteristics.

Abstract: A set of a digital indicating circuit and an indicator are connected to digital clock circuit means and desk computer calculating circuit means through switching elements, a flipflop, and a switching key so as to be commonly used in both digital clock and desk computer. Power circuit means is connected directly to the digital clock circuit means, and to the desk computer circuit means through the switch so that the digital clock circuit is at all times supplied with electric current.

Abstract: A testing process is described for stress testing each gate electrode in a dynamic random logic FET circuit array incorporated in an LSI device. The process comprises the steps of providing operating potentials and clock signals to each logic circuit in a logic path in the LSI device; providing a stress voltage to each initial logic element in a logic path, and sequencing the clock signals to each logic circuit in reverse order to that sequence required to transfer information through a logic path to perform the circuit logic function. The invention advantageously utilizes the fact a reverse clock will sequentially stress each logic circuit while in a discharge state and the other logic circuits are in a non-conducting condition.

Abstract: A master clock having an oscillator, a divider, a signal shaper, an output amplifier, and power feed either by means of an electric circuit or by means of a battery at the time of power failure in the circuit. A detector for circuit voltage is provided which upon a fall in circuit voltage switches signals from the output of the divider to an electronic memory. Upon reestablishment of power in the circuit, the time signals are fed out of the memory at an accelerated rate to cause the secondary clocks controlled by the master clock to catch up. It is thus possible to use only a small and inexpensive standby battery for use during power failure.

Abstract: A four-phase logic system is provided which includes at least four logic networks connected in parallel between a single power line and a reference potential. A four-phase clock generator generates four distinct clock signals from a single-phase clock input at data rate. Each logic network comprises a pair of complementary metal-oxide-semiconductor integrated transistors (CMOST). Each metal-oxide-semiconductor transistor (MOST) in the pair is responsive to a clock signal which turns the transistor ON or OFF. In each network there is also at least one MOST which is responsive to a logic signal. The logic transistor is connected in cascade with the pair of CMOSTs. A stray capacitance which serves as a storage capacitor between the junction of the pair of transistors and a reference potential provides an output signal dependent upon the applied clock signals and the incoming logic signal.

Abstract: A dynamic logic interconnection comprises a plurality of individual logic circuits connected in series, the individual logic circuits including a diode element in series with the controlled current path of an active circuit element, to which individual circuits single phase clock pulses are applied at the same time.

Abstract: Disclosed is a calculator system featuring a precharged carry propagate arithmetic logic circuit. A plurality of data registers store in parallel a plurality of multi-bit data words and are coupled in parallel to the arithmetic logic circuit for executing arithmetic and logic operations thereon. The arithmetic logic circuit is responsive to instruction words for executing either an addition or a subtraction function. A carry propagate circuit is provided for precharging a carry terminal of each bit in the ALU to a reference potential along with a circuit associated with each bit for selectively discharging the carry terminal responsive to the logic level of the previous carry signal into each bit and is further responsive to the appropriate bits of the data words. An exclusive-or adder circuit has an adder terminal precharged to a reference potential during one phase of a clock signal, and further has a discharge circuit for selectively discharging the terminal in response to logic levels of the appropriate bits of the data word and responsive to the carry signal.

Abstract: A simple technique is presented for using standard IC logic elements to synthesize frequencies. In particular, certain fractional multiples of a primary frequency may be synthesized for which no convenient techniques are available at digital logic levels. By utilizing the harmonic content of repetitive digital waveforns, sum and difference frequencies may be extracted from the output of the digital logic network. In effect, the new technique provides a type of digital mixing to accomplish frequency synthesis (or conversion) which is compatible with modern digital circuits. The circuit complements available techniques for division by an integer.

Abstract: A photographic flash firing circuit operative to sequentially ignite each of an array of flash lamps in a predetermined order from first to last responsive to an input signal. The circuit is constructed as an integrated circuit including a dual set of circuit components capable of being interconnected for either low level, logic triggering or pulse triggering of the circuit. Basically, the firing circuit includes a plurality of lamp switching circuits and a forward sequencing circuit which sequentially couples each lamp across a supply voltage in accordance with repetitive activation by a suitable trigger network. In the logic trigger arrangement, the trigger network includes a transistor buffer stage and voltage divider network coupled to the forward sequencing circuit and operative to trigger the latter in accordance with operation of the camera exposure control system.

Abstract: Recently, Tan developed a heuristic state assignment algorithm for asynchronous sequential machines. In this paper a state assignment algorithm based on Tan's is developed for synchronous sequential machines. It shares with Tan's algorithm the advantages of simplicity of execution and economy of logic elements in the resulting realizations.

Abstract: This correspondence is concerned with the use of inertial delay elements for the correction of influences of aith-order hazards and races among internal signals on the activity of asynchronous sequential circuits

Abstract: The characteristics of combinational and sequential circuits or networks can be expressed in ‘transition-equation’ form. Transition characteristic equations carry complete information on the behaviour of the circuit, and are readily derived for any circuit or from any reasonable circuit data sheet. Synchronous, clock and asynchronous inputs can be shown, and also the nature of the clock activation, where appropriate. Propagation delays may also be manipulated with the characteristic expressions. Network characteristics can also be expressed in terms of desired transitions from one state to another, and this leads to straightforward synthesis procedures when circuit characteristics are in transition-equation form. Analysis is equally straightforward. The paper briefly introduces transition characteristic equations by way of J-K flip-flops and NAND gates, and then uses a simple example to illustrate the approach to synthesis. It is clearly shown that the transition equations allow for several different approaches to be taken to the same problem. Hazards due to propagation delays are also revealed, which is particularly helpful, for example, when dealing with ‘ripple-through’ arrays.

Abstract: A new type of monostable circuit, based on the novel interconnection of a complementary transistor bistable circuit and a long-tail-pair comparator, is described. The power consumption in the stable state of the circuit is only a few nanowatts, thus making the scheme particularly suitable for aerospace, telemetry, biomedical and mobile radar applications. The circuit gives accurately predictable output pulses with pulse widths as low as 0.2 mu s, which are relatively immune to supply voltage variations. The maximum mark-space ratio is approximately 1:5. With suitably chosen transistors the circuit can operate over a rail supply voltage range from 3 to 30 V, and is simply triggered from standard digital integrated circuit logic.

Abstract: A memory element such as a random-access (r.a.m.) may be used as a variable-logic device, the logic function being found between the address terminals and the output. This paper discusses design techniques whereby a single system of such memory elements may be used to implement several logic functions. The question of training or programming such systems is also considered with particular reference to cases in which the system is required to imitate another operational circuit. To this end a concept of `trainability' is introduced and it is shown that this is a nontrivial parameter that has to be taken into account at the design stage. Trainability tests are introduced and techniques for deriving training sequences for trainable systems are derived.

Abstract: The modification of a programmable read only memory circuit One or more of the outputs are supplied as feedback signals to corresponding inputs transforms the conventional read only memory circuit into a circuit capable of memory and sequential logic functions

Abstract: A sequential data transmission system such that an instruction for slow-sequence operations being inserted into a program of fast-sequence operations controlled by a pulse counter. The same is controlled by a clock and associated with sequence switch. The system is characterized in that when a slow sequence is triggered, the counter produces the zero state at the output of a first logic operator connected to the input of a pulse-shaping circuit whose output is connected to the first input of a second logic operator, the same having two inputs. The second input of the second logic operator is connected to a normally open relay contact which closes upon termination of the slow-sequence operation. The output of the second logic operator is connected to an input of a bistable and causes the output thereof to take up a fixed logic state if the pulse-shaping circuit is operative and if the relay contact is open. This fixed logic state blocks the pulse counter by way of a third logic operator; and the bistable positioned in accordance with the foregoing is reset by a signal which is synchronous with but offset from the clock signal.

Abstract: The automation of a method for synthetising asynchronous sequential circuits is reported. The method is suitable for circuits having transition and level inputs. Inclusion relations between state-pair sets and partitions are used for the selection of suitable partitions for an economic race-free state assignment of minimum transition time.

Abstract: A simple frequency latch for use as a logic circuit building block in which two or more signals of predetermined frequency are fed into narrow-band amplifiers and mixers. When all input signals are present, they are mixed together and the mixed signal is fed back to the inputs to shut off further input signals. The mixed signal is stored in the circuit by means of an oscillation loop.