Abstract: A generalized and modular logic circuit for arithmetic/logical units of a digital computer, adaptable to large scale integration (LSI) manufacturing techniques. Each logic circuit includes combinational logic networks which provide inputs to storage circuitry. The storage circuitry is sequential in operation and employs clocked dc latches. Out-of-phase clock trains are used to control the latches. With each storage circuit, there is provided additional circuitry for providing an input which is independent of the combinational logic network. A logic unit comprised of a plurality of the logic circuits is constructed to interconnect the output of a storage circuit to the independent input of another logic circuit so that each latch acts as one position of a shift register having inputs/outputs independent of the system inputs/outputs.

Abstract: Disclosed are universal associative logic circuits for use in designing digital systems. The logic circuits comprise an array of storage cells interconnected to form a final circuit configuration which can be electrically altered to make possible the generation of a plurality of logic functions which may be specified after fabrication of the circuit. Programming means are provided to configure the circuit so that it can generate signals representative of a required Boolean function or functions, each function having a single or a multiplicity of output signals and including both combinational and sequential logic forms.

Abstract: An inverting binary-charge regenerator for use with new charge- transfer devices (charge-coupled and integrated MOS bucket brigade) is described. This simple element requires an area approximately that of one bit in the register and is driven by the transfer pulses. Its uses with these shift registers in various configurations, which are described, make possible even larger functional devices. These uses include regeneration in serial memories, performing logic operations such as NAND and NOR involving the bit trains in several registers, and performing fixed counts and sequential addressing of other circuit elements.

Abstract: A printed circuit card tester for dynamically testing digital logic circuits on a visual GO/NO-GO basis is described. A repetitive set of waveforms is supplied to the circuit under test as stimuli therefor. Digital logic circuitry performs analysis of an output from the circuit under test which involved the counting of predetermined numbers of clock pulses during preselected timing intervals to determine the precise time interval between distinct edges (transitions) of the output from the circuit under test and to provide GO/NO-GO indications while the circuit under test is being dynamically exercised.

Abstract: Digital logic simulation is the process whereby the action of a logic circuit due to a specified input is predicted based upon some model of the circuit. Logic simulation is becoming increasingly necessary as larger and more complex computers are built. Because of the cost of building hardware it is not wise to commit a circuit design to manufacture without first verifying the operation of the circuit by simulation. This is true even for large computers (say 50,000 gates) where simulation will eliminate many logic errors and may save construction of a prototype model. Simulation may be used to predict the output of the circuit due to specified faults as well as to predict the output of the good (fault free) circuit. A dictionary is generally compiled of the output of the circuit in the presence of known faults. By comparing the actual (perhaps faulty) circuit output to the correct output, it is possible to detect and diagnose a fault in the circuit.

Abstract: A circuit arrangement for synchronizing transmitters and receivers in data transmission systems to facilitate the transfer of blocks of data constituted by information bits and parity bits is described. In the receiver the bits are serially entered into a shift register. A testing circuit is provided which, after supplying a testing clock signal, emits an output signal when the bits in the shift register pertain to the same data block. Testing circuits may be individually connected to stages in the shift register, and the testing signals are generated responsive to the presence of information or parity bits in the various register stages. Clock generators are provided for producing data block clock signals with as many block clock signals being produced as there are possible positions in the data blocks. The block clock signals are supplied to the testing circuits as testing clock signals via outputs of the clock generators. The testing circuit outputs are connected to counter inputs, and the counter outputs are connected to a logic circuit. The logic circuit determines the correct block clock signal in relation to the counter output signal.

Abstract: Means are provided for rapidly, completely, and substantially automatically checking the integrity of the logic and related circuitry employed to control and direct the initiation and termination of combustion at elevations of burners in a furnace. The existing burner control logic is utilized in the generation of substantially all of the input signals to remaining logic under test. The driven devices, such as burner guns, fuel valves, etc., are prevented from responding to their command signals supplied by the control logic. These command signals appearing at the outputs from the control logic system are indicative of proper operation of the logic required to produce them. The feedbacks to the control logic from the sensing devices associated with the driven devices are operative to indicate the fact that the disabled driven devices have not responded correctly to input commands during startup and to effect the necessary commands resulting in a shutdown sequence of the control logic. Means are provided for simulating the two or three signals required for proper sequential operation of the logic which fail to appear when the existing logic is operated in a test mode.

Abstract: The asynchronous signal is complemented and directed to a latching logic circuit as the data input and the synchronous signal are directed to the clock input of the latching circuit. The latching circuit has built-in delays to reliably latch if the low or active portion of the asynchronous pulse occurs during the "window" or high portion of the synchronous signal. The latching circuit also includes a jamming circuit connected to its clock input whereby a low or disabled window time of the synchronous signal prevents a change in state by the latching circuit. A pulse delay circuit generates a sampling pulse a period of time after the window time to sample the output of the latching circuit.

Abstract: An interference suppression device for logic signals including two logic units in series with periodically controlled storage of an information signal and later transmission thereof to an output terminal, and at least one regenerating circuit which when supplied with identical information at its inputs switches the units to a definite state thus maintaining an information signal at the output of the suppression circuit.

Abstract: A novel booster circuit is disclosed which is effective to improve high and low frequency performance of synchronous MOS logic circuits. In a preferred embodiment, the circuit is effective to boost a logic ''''1'''' output from a logic stage by capacitively coupling a clock signal thereto just prior to sampling. The coupling capacitor comprises an MOS device having its gate connected to the output node, the clock signal source being selectively connected to the output circuit thereof through a switching device controlled by the level of the output signal. Upon the occurrence of a logic ''''1'''' output the gate to channel capacitance of the MOS device serves as a large coupling capacitance to which the clock signal is thereafter applied to boost the logic output prior to sampling by the next logic stage.

Abstract: A logic circuit with a redundant element is particularly characterized in that an associative memory element is additionally provided which is to electronically connect a redundant element with the logic circuit

Abstract: A three transistor exclusive-OR logic circuit is disclosed in which only three of the four possible logic levels of the two input variables are needed.

Abstract: A firing circuit for providing time zero crossing firing of a load-controlling SCR, adapted particularly for firing a load-controlling SCR connected in circuit relationship in a single phase of a multi-phase electrical system, including an electrical power supply, a first quad section integrated circuit means connected in circuit relationship with the power supply and including a first flip flop and a second flip flop, a second dual section integrated circuit means connected in circuit relationship with the first integrated circuit means, a photo isolator to accept a logic input from another logic system and including at least one light emitting diode connected in circuit relationship with the aforesaid logic system and a photo transistor coupled to the light emitting diode and connected in circuit relationship with the first and second integrated circuit means, and a load-controlling SCR connected in circuit relationship with the first and second integrated circuit means such that zero crossing firing of the SCR is provided in accordance with a two step process which is initiated when a logic input is fed to the firing circuit through the photo isolator and regardless of when during the cycle the logic input is supplied.

Abstract: A shift register-decoder circuit is adapted to preset the memory location in the data storage section of a permanent storage memory from which data is initially transferred to an output node. That circuit comprises a shift register having a plurality of stages and a corresponding plurality of logic decoder circuits. The logic decoder stages are operatively associated respectively with a plurality of column output nodes and are adapted in response to an input address signal to initially uniquely charge a selected one of said column output nodes. Subsequently, the logic decoder circuit is disabled and the shift register is enabled and is effective to shift the column select signal sequentially to successive columns under the influence of an external clock signal. The resulting data scanning operation continues until the memory is disabled by the operation of a disabling circuit.

Abstract: A single line per bit logic circuit serves as one of plural cascaded stages in a binary register through which data characters are shifted asynchronously, serially by character, parallel by bit. Each stage has a neutral state (no stored information) and an information state (stored information). Control logic in each stage controls shifting as follows: stage i receives information from stage (i-1) only if stage (i-1) is in its information state and stage i is in its neutral state; likewise, stage i shifts information to stage (i+1) only if i is in its information state and stage (i+1) is in its neutral state. A single line per data bit configuration is made possible by rendering the shift control logic independent of the data bits. In one embodiment, each circuit stores four parallel bits, the shifting of which is controlled by independent logic circuitry in that circuit.

Abstract: A modified MOST invertor circuit consisting of a driver, load, and bias MOST is proposed. The gate voltage of the load MOST is supplied by the bias MOST. This leads to an improvement of both the output pulse height and the switching speed if the circuit is applied in dynamic logic. The switching transients are studied by considering first the dynamic loadlines of the driver and the load MOST, and second an analytical function has been developed predicting the 10-90 percent turnoff time of the circuit. The theoretical turn-off times are found to be in agreement with measurements on a breadboard circuit and from this a maximum gain in 10-90 percent turn-off time of the modified invertor of about a factor of 3, as compared with a conventional MOST invertor, appears to be attainable. The modified invertor circuit may also be used in static logic with conservation of its full advantages, provided that the minimum switching period is about 50 ns.

Abstract: A circuit for interference free recognition of zero crossings of differentiated read signals comprises a zero detector and a signal checking circuit for simultaneously receiving the read signals. The signal checking circuit comprises an amplitude evaluation circuit and a time evaluation circuit. The zero detector and the signal checking circuit are connected to an output circuit which provides an output pulse in response to an output signal from the zero detector and the signal checking circuit. The time evaluation circuit comprises a charging circuit including a capacitor which is charged in accordance with a first time constant when a differentiated read signal exceeds an amplitude evaluation level of the amplitude evaluation circuit and is discharged in accordance with a second time constant when the differentiated read signal is lower than the amplitude evaluation threshold.

Abstract: When the gating signal and clock pulses applied to a gated dividing circuit are unsynchronized, the first output produced by the circuit can appear any time within a time period equal to the intervals between the clock pulses. This time period is reduced, in accordance with the present disclosure, by using more than one such circuit, applying delayed versions of the clock input to the added circuits, and then combining the circuit outputs so that an output is produced whenever a predetermined number of the circuits produces a particular output.

Abstract: An echo suppressor that is composed solely of digital logic circuits and based on a digital voice detector [1] has been designed The unit is simple and requires no adjustment Its basic application is to the SPADE [2] PCM channel, although it can be adapted to work with other systems Results of initial subjective tests are included

Abstract: Disclosed is a storage-processor element, designed so that groups of such elements can be interconnected into threshold logic circuits. Each element is arranged to decide which one of a pair of double-rail input signals has a higher potential and to store the result of that decision. Information read out of storage directs a unit of current to one or the other of two output busses. A threshold logic adder circuit and a threshold logic two''scomplement circuit use combinations of the storage-processor elements.

Abstract: A clock supplies clock pulses at a predetermined frequency. A group of controlled switching circuits are interconnected between the d-c supply source and the load, typically the windings of a polyphase a-c asynchronous motor. The controllable semiconductor switching circuits are controlled from the clock source to be switched between ON and OFF state to selectively, sequentially energize the windings of the motor. To provide better approach of the pulses to sinusoidal wave shape, a delay circuit is connected between the controlled semiconductor switching circuit to delay the trailing flanks of the pulses passed by the switching circuit upon change from ON to OFF of the semiconductor switches.

Abstract: Medium scale integrated circuits and logic gates are connected to provide sequential output instructions, responsive to a predetermined sequence of logic states contained in a decoder, and in synchronization with clock pulses.

Abstract: A new scheme for fault restoration in logic circuits using N-fail-safe logic is proposed. Its failure probability is shown to be significantly less than those of the majority voting scheme and quadded logic, although the cost of realization is comparable to both.

Abstract: The operation of analog memory systems utilizing semiconductor charge-transfer devices is controlled by a control logic circuit including clock control logic, recirculation control logic and mode selector control logic. The clock control logic includes a first switch for selecting the repetition rate of bursts of clock pulses which read the analog input information signal into the memory unit of the system and a second switch for selecting the number of clock pulses in the burst. The recirculation control logic includes a switch for obtaining recirculation of the stored information and selecting the number of recirculations between successive read-ins of new analog information. The mode selector control logic determines the mode (read-in or recirculate) of operation of the memory system.

Abstract: A numerical control system for moving a controlled member along a given axis includes a digital to analog converter and a logic circuit to increase the resolution of the digital to analog converter. The logic circuit subdivides adjacent counts retained in the logic circuit by varying the amount of time during which the respective counts are directed to the digital to analog converter. The counts retained in the logic circuit differ by a fixed amount, and the magnitude of these counts is dependent upon the input pulse frequency applied to the logic circuit.

Abstract: A plurality of flip-flops are serially connected into a ring by switches which are controlled by a one-phase clock pulse and its logical complement. In response to the one-phase clock pulses there are produced multiple-phase control signals with controllable partial overlap of successive phases. The overlap is equal to the width of the one-phase clock pulse. The apparatus is especially useful for providing three-phase clock pulses for driving charge coupled devices and is readily integrable in the form of standard logic gates.

Abstract: : In this paper the authors present several techniques to design asynchronous sequential networks. It is assumed that the asynchronous sequential machines to be realized are described by normal mode flow tables; also, that only single input variables changes occur and that the state variables (feedback variables) are delayed appropriately such that essential hazards need not be considered. The fault model for the design techniques and necessary and sufficient conditions on the state assignments for m-fault-tolerant asynchronous sequential networks are given. Three design techniques for the fault-tolerant networks are given.

Abstract: A read head for an optical character-recognition system including a plurality of photodetectors coupled to at least two shift registers, clock signals for activating the shift registers, and a logic circuit for interconnecting the shift registers. By varying the arrangement of the logic circuit elements, the read head can be adapted for a plurality of scanning modes used in conjunction with optical characterrecognition systems. The logic circuit suppresses false data groups introduced by spurious photodetector signals.