Abstract: A system and method for implementing one or more specific purpose rule-based n-bit virtual processing machines. Specific purposes include, but are not limited to, encryption, compression, and arbitrary precision arithmetic. Each virtual machine consists of a command processor, a rule-base, and an interface between the command processor and the rule-base. Each of the elements of a specific purpose rule-based n-bit virtual machine--the command processor, the rule-base, and the rule-base interface--is preferably implemented as software. In the preferred embodiment, the system uses a stored rule-base as its instruction set and provides for input and output in the form of variable length bit strings of length n where n is any number greater than zero. Each of the rules within the rule-base performs one or more binary string operations against one or more variable length n-bit strings. The function of the rule-base is to provide a set of application specific rules that allows the machine to perform a particular task such as encryption, data compression, or arbitrary precision arithmetic. The system includes a method for providing a software interface to the rule-base. This interface may be a separate program or may be contained within the command processor. The command processor receives input in the form of one or more n-bit data types, performs rule-based operations on the data, and returns output in the form of one or more n-bit data types. Specific system and methods for performing data encryption, data compression, and arbitrary precision arithmetic using the invention are described.

Abstract: A data processing system incorporating an arithmetic logic unit (20, 22, 24) having an N-bit data pathway and supporting parallel operation program instruction words in which to independent arithmetic operations are carried out in parallel by the arithmetic logic unit upon (N/2)-bit input operand words. Two sets of condition code flags N, Z, C V, SN, SZ, SC, SV responsive to the separate arithmetic logic operations are provided.

Abstract: There is propound the check by modulo method of multiplier with the abridgement of computation, that is in high-performance floating-point arithmetic devices. The forming of uncalculated part of the operation result by processing of small capacity check codes of the operands and their parts is on the basis of the method. It provides simplicity of the check circuit for which equipment expenses are in linear depending on the capacity of operands under condition squaring dependence of expenses of the main equipment.

Abstract: A microprocessor circuit is disclosed for instructions on an arithmetic/shift function performing standard operations (e.g., ALU instructions or Shift instructions) on instructions in a first cycle of operation, and a correction circuit responsive to the arithmetic/shift function for modifying the standard results provided by the arithmetic/shift function to results required by a SIMD instruction being executed. The arithmetic/shift function is an instruction provided by either an Arithmetic Logic Unit (ALU) or by a shift instruction. The correction circuit passes data, unchanged for logical instructions but provides condition codes according to the SIMD instruction.

Abstract: This chapter presents the design and analysis of variable-precision, interval arithmetic processors. The processors give the user the ability to specify the precision of the computation, determine the accuracy of the results, and recompute inaccurate results with higher precision. The processors support a wide variety of arithmetic operations on variable-precision floating point numbers and intervals. Efficient hardware algorithms and specially designed functional units increase the speed, accuracy, and reliability of numerical computations. Area and delay estimates indicate that the processors can be implemented with areas and cycle times that are comparable to conventional IEEE double-precision floating point coprocessors. Execution time estimates indicate that the processors are two to three orders of magnitude faster than a conventional software package for variable-precision, interval arithmetic.

Abstract: In many applications where logic functions need to be analyzed it can be useful if we transform Boolean (or switching) functions to arithmetic functions. Such arithmetic transformations can give us new insight into solving some interesting problems. For example, the transformed functions can be easily evaluated (simulated) on integers or real numbers. Through such arithmetic simulation we can probabilistically verify a pair of functions with much more confidence than two-valued Boolean simulation. The arithmetic transform of any Boolean function can be easily computed from its BDD. To help evaluate a Boolean function on non-binary inputs, and to represent multi-variable linear polynomials with integer coefficients, a BDD like data structure snDD can be used; for many arithmetic expressions, snDDs are a very compact representation. The error in such probabilistic verification of property of a function is quantifiable and extremely low. Also, the procedures are computationally very efficient. Using a real-valued or integer-valued representation we can derive testability measures for elements of a digital circuit, or conduct the reliability analysis for various networks.

Abstract: Recoding is the process of transforming between digit sets. It is used to reduce the cost and delay of the implementation of arithmetic algorithms, such as digit-recurrence and parallel algorithms for multiplication, division/square-root, and in compound operations. We present a simple and systematic basis for developing these recodings.

Abstract: The result of a simple floating-point computation can be in great error, even though no error is signaled, no coding mistakes are in the program, and the computer hardware is functioning correctly This paper proposes a set of instructions appropriate for a general purpose microprocessor that can be used to improve the credibility and accuracy of numerical computations Such instructions provide direct hardware support for monitoring events which may threaten computational integrity, implementing floating-point data types of arbitrary precision, and repeating calculations with greater precision These useful features are obtained by the efficient implementation of high radix on-line arithmetic The prevalence of super-scalar and VLIW processors makes this approach especially attractive

Abstract: In classical and intuitionistic arithmetics, any formula implies a true equation, and a false equation implies anything. In weaker logics fewer implications hold. In this paper we rehearse known results about the relevant arithmetic R#, and we show that in linear arithmetic LL# by contrast false equations never imply true ones. As a result, linear arithmetic is desecsed. A formula A which entails 0 = 0 is a secondary equation; one entailed by 0 ≠ 0 is a secondary unequation. A system of formal arithmetic is secsed if every extensional formula is either a secondary equation or a secondary unequation. We are indebted to the program MaGIC for the simple countermodel SZ7, on which 0 = 1 is not a secondary formula. This is a small but significant success for automated reasoning.

Abstract: The speed of integer and rational arithmetic increases significantly by systolic implementation on a SIMD architecture. For multiplication of integers one obtains linear speed-up (up to 29 times), using a serial-parallel scheme. A two-dimensional algorithm for multiplication of polynomials gives half-linear speed-up (up to 383 times). We also implement multiprecision rational arithmetic using known systolic algorithms for addition and multiplication, as well as recent algorithms for exact division and GCD computation. All algorithms work in “least-significant digits first” pipelined manner, hence they can be well aggregated together. The practical experiments show that the timings depend linearly on the input length, demonstrating the effectiveness of the systolic paradigm for multiple precision arithmetic.

Abstract: This paper presents a high-speed fully signed-binary (SE) parallel multiply-accumulate (MAC) arithmetic architecture. This arithmetic architecture employs a novel 5-digit overlapped scanning technique for the modified radix-4 recoding of the constituent SE multiplier. The proposed scanning technique permits a reduction in the number of the intermediate partial product components generated during the course of MAC arithmetic operation by a factor of two, leading to a fast processing speed at reduced hardware cost. The resulting MAC arithmetic architecture performs full-precision accumulation, rounding, and overflow correction concurrently in order to facilitate a high-speed overall operation. A high-performance architecture is also presented for IEEE Standard 754 default rounding of the final SE MAC result. The proposed MAC arithmetic architecture is parameterized for ASIC implementations using the Actel 1.2 /spl mu/ technology parameters, and is subsequently verified by using Viewlogic simulations.

Abstract: Numbers describe form and complexity, in addition to quantity and order. In this manner arithmetic can be interpreted as the natural logic of objective processes and of rational thinking.

Abstract: The unique relationships between Arithmetic spectra of switching functions and the spectra of Boolean AND, OR and XOR of such functions are presented. Essential operations used in classification and optimization of logical network have been also analyzed in Arithmetic spectral domain. Some of such operations involve input and output negations and permutations of input variables. By using presented methods, the computation of the total spectrum of any Arithmetic expression for an equivalent switching network is straight forward, and many of the equivalent operations in Arithmetic domain are simpler than their Boolean counterparts which should increase practical interest in usage of Arithmetic transform for design automation tools.

Abstract: Many potential applications for veconfigurable computing need the dynamic range provided by floating-pointarithmetic. However, doing floating-point on FPGAs is difficult because of the large amount of hardware required,particularly for multipliers. Some limited success has been obtained through digit-serial implementation of IEEEfloating-point multipliers, but the IEEE representation is not easily or efficiently implemented in serial form.Therefore, we have been exploring alternate number representations. Signed-digit representations have shown some promise, since their form lends them to serial computation, which consumes much less hardware thanfully parallel approaches. We show how the signed-digit representation can be used to implement floating-point arithmetic, and we present prototype implementations using Altera FPGAs. Keywords: FPGAs, hardware accelerators, custom computing machines, arithmetic, floating-point arith- metic, signed-digit arithmetic 1 INTRODUCTION Many potential applications for reconfigurable computing need the dynamic range provided by floating-point

Abstract: Multiple precision arithmetic forms the core of symbolic computation systems. A speedup of the basic algorithms can therefore improve all higher-level algorithms. Several packages have been developed for sequential processors. Although they were implemented carefully, they are unsatisfactory for large inputs. Performance can be improved by chosing algorithms with better asymptotic behavior or by using other computing models such as parallel machines.

Abstract: By algebraic means, we give an equational axiomatization of the equational fragments of various systems of arithmetic. We also introduce a faithful semantics according to which, for every reasonable system T for arithmetic, there is a model where exactly the theorems of T are true.

Abstract: The concept of Mixed Arithmetic Logic and Expansions is introduced in this paper. The recursive ways of generating Forward and Inverse Fast Transforms for Mixed Arithmetic Logic are presented. The paper describes basic properties and lists those Mixed Arithmetic Transforms which have convenient fast forward algorithms and easily defined inverse transforms. Finally, the computational advantages and usefulness of new expansions based on Mixed Arithmetic Logic in comparison to known Arithmetic expansions are illustrated on some examples.

Abstract: An arithmetic processing method and arithmetic processing device each which can reduce the number of logical stages needed to obtain the final arithmetic result, thus executing an arithmetic process such as a floating-point multiplication at high speed to reduce the arithmetic process time. According to the arithmetic processing method and arithmetic processing device, the possibility that an arithmetic exception occurs in the arithmetic result obtained through an arithmetic process is judged in the middle of the arithmetic process of the dedicated arithmetic processing unit. Transmitting an arithmetic end signal to the instruction control unit is inhibited when it is judged that there is a possibility; the arithmetic process with the possibility is executed by means of another arithmetic unit different from the dedicated arithmetic unit. Thereafter the arithmetic end signal regarding the arithmetic process is transmitted to the instruction control unit. The arithmetic processing method and arithmetic processing device can be applied to the case where an arithmetic process such as a floating-point arithmetic operation is performed in a pipeline mode.

Abstract: We propose and demonstrate a multiwavelength arithmetic logic unit in photorefractive media wherein the polarization states of optical waves are used to encode the binary numbers 1 and 0. The process of writing and reading of photoinduced gratings in photorefractive media is utilized to implement and/or logic gates and an arithmetic full adder, which are the key elements of an arithmetic logic unit. To take advantage of wavelength-domain parallelism and to reduce the hardware needed for multibit operations, optical wavelengths are used to represent specific bits of binary words. Because of the broad bandwidth of optics, multiwavelength operations can be realized simultaneously within a single crystal. In this way, multibit operations can be performed in a single arithmetic logic unit. Experimental results are presented and discussed.

Abstract: The results of a research project conducted at Gandalf, a leader in real time data networking products, to develop a fast arithmetic coder are presented. The speed improvement comes from the development of a hybrid model that generates normalized frequency distributions of the sequence of input symbols. This approach enables the implementation of an arithmetic coder with a reduced number of divide instructions. The new coder obtains significantly improved throughput with minimal loss in compression efficiency. Simulation results showed a doubling in computational speed over standard implementations of the algorithm with minimal reduction in efficiency. The algorithm achieves up to 50% more compression efficiency than the commercially available Stacker LZS compressor.

Abstract: This paper is concerned with the derivation of the relationship that exists between the number truncation in two's complement (TC) arithmetic and the corresponding truncation in signed-binary (SB) arithmetic. The resulting relationship is subsequently exploited and applied to the development of a pair of novel techniques for SB rounding. These techniques are then translated into algorithms suitable for two-level logic implementation. Finally, the resulting algorithms are applied to the design and implementation of a high-speed SB-kernel based TC multiply-accumulate arithmetic architecture.

Abstract: The lattice wave digital filter (LTWDF) is known to be especially suitable for high speed filtering applications, owing to the low wordlengths required. The authors present a comparison between several LTWDF architectures using redundant and non-redundant arithmetic. It is shown that architectures using non-redundant arithmetic require up to 2.5 times less VLSI area, while offering higher sample rates for most practical filtering applications.

Abstract: The logarithmic number systems (LNS) have long been used in arithmetic to simplify processes such as: multiplication to addition, division to subtraction, and powers to multiplication, etc. A difficult problem may arise from the accuracy of conversion during the processing operations and a very large number of product terms should be generated if a look-up table is realized by a ROM. In some cases, it may be impossible to use such a large capacity ROM (say, 2/sup 24//spl times/24) if no partitioned scheme is used. This paper presents a four-partition conversion scheme in order to be implemented by small sized ROMs. It can generate better results and higher speed conversion comparing with previous methods for two- or three-partition schemes. This algorithm can also be used in conversion of antilogarithms.

Abstract: A family of mixed arithmetic logic whose transform matrices possess fast algorithms is introduced. The mixed arithmetic transforms are applied to multiple-valued input binary functions. The paper describes basic properties and lists those mixed arithmetic transforms which have fast forward and easily defined inverse transforms. Finally, the advantages of mixed arithmetic logic spectra for some multiple-valued input binary functions are shown.

Abstract: PROBLEM TO BE SOLVED: To increase the drawing speed without increasing the hardware capacity by preparing the arithmetic parts which exclusively perform the matrix and a product-sum operations respectively. SOLUTION: An instruction cache memory 112, a data cache memory 113, a geometric arithmetic part 114 which primarily performs the matrix and function operations such as the coordinate transformation, etc., and a physical arithmetic part 115 which constructs a DDA(digital differential analyzer) are connected to a CPU main body 111 via an internal bus 110. In such a constitution, a main CPU can perform its processing to some extent without using a main bus 10. Thus, the bus 10 can be easily opened. The parts 114 and 115 consist of the arithmetic processing parts 114P and 115P and the register packets 114R and 115R respectively and can perform each arithmetic processing in every packet. A DDA array constructing the part 115P consists of plural adders and registers.

Abstract: IEEE floating-point arithmetic standards 754 and 854 reflect the present state of the art in designing and implementing floating-point arithmetic units. A formalism applied to a standard non-trapping mode floating-point system shows incorrectness of some numeric and non-numeric results. A software emulation of decimal floating-point computer arithmetic supporting an enhanced set of exception symbols is reported. Some implementation details, discussion of some open questions about utility and consistency of the implemented arithmetic with the IEEE Standards are provided. The potential benefit for computations with infinite symbolic elements is outlined.