Abstract: The problem of evaluating the sign of the determinant of a small matrix aries in many geometric algorithms. Given an n*n matrix A with integer entries, whose columns are all smaller than M in Euclidean norm, the algorithm given evaluates the sign of the determinant det A exactly. The algorithm requires an arithmetic precision of less than 1.5n+2lgM bits. The number of arithmetic operations needed is O(n/sup 3/)+O(n/sup 2/) log OD(A)/ beta , where OD(A) mod det A mod is the product of the lengths of the columns of A, and beta is the number of 'extra' bits of precision, min(lg(1/u)-1.1n-2lgn-2,lgN-lgM-1.5n-1), where u is the roundoff error in approximate arithmetic, and N is the largest representable integer. Since OD(A) >

Abstract: A residue number system to binary converter that converts numbers in the moduli set 2n+1,2n,2n-1 is described. This moduli set is an extension of the more popular set, 2/sup n/+1, 2/sup n/, 2/sup n/-1. A low-complexity implementation using some properties of modular arithmetic is proposed. The converter does not use any explicit modulo operation in the evaluation as is normally done in the Chinese remainder theorem. >

Abstract: An arithmetic is described that can replace floating-point arithmetic for programming tasks requiring assured accuracy. A general explanation is given of how the arithmetic is constructed with C++, and a programming example in this language is supplied. Times for solving representative problems are presented.

Abstract: Robustness in geometric computation is an important subject and it the topic of a variety of research by many people. Yet, to date, there is no known provably robust algorithm for performing Boolean operations on solids. The primary difficulty lies in performing arithmetic operations where fixed precision floating point numbers are employed to carry out operations that require infinite precision. Consequently, topological decisions based on the results of finite arithmetic operations are error prone. We study the robustness problem in the context of Boolean operations on solids by implementing a solid modeler that is capable of performing both rational arithmetic and floating point arithmetic. The algorithm has been implemented in identical code except for arithmetic. Therefore, it clearly demonstrates the effects of numerical errors on Boolean operations in those cases where the algorithm produces correct results with rational arithmetic but fails with floating point arithmetic. We analyze spatial configurations of solids that could result in failure of Boolean algorithms when floating point arithmetic is adopted. With inevitable numerical errors in floating point arithmetic, it seems attractive to use rational arithmetic when implementing Boolean algorithms. However, as shown by the classification operations, this is feasible only when dealing with linear objects such as lines and planes. We study the precision required for exactly classifying a point, defined as the intersection of two lines or three planes, with respect to a given line or plane. Assuming line and plane equations have bounded integer coefficients, we need roughly four and five times of the input precision for point/line and point/plane classification respectively and we also show that this result is optimal. Next we extend the concept of exact classification to the curve and surface domain. We study a resultant based method to exactly classify a point with respect to a given conic or quadric. The required precision is shown to be too high to be practical. Using piecewise linear approximations of conics and quadrics, the same problem is reduced to the exact point/line or point/plane classification problem which has previously solved. The required precision of the approximations is also analyzed.

Abstract: A computer program to honestly plot curves y = $(x) must locate maxima and minima in the domain of the graph. To do so it may have to solve a classic problem in computation – global optimization. Reducing an easy problem to a hard one is usually not an advantage, but in fact there is a route to solving both problems if the function can be evaluated using interval arithmetic. Since some computer algebra systems supply a version of interval arithmetic, it seems we have the ingredients for a solution. In this paper we address a particular problem how to compute and display “honest” graphs of 2-D mathematical curves. By “honest” we mean that no significant features (such as the location of poles, the values at maxima or minima, or the behavior of a curve at asymptotes) are misrepresented, By “mathematical” we mean curves like those generally needed in scientific disciplines where functions are represented by composition of common mathematical operations: rational operations (+, –, *, /), exponential and log, trigonometric functions as well as continuous and differentiable functions from applied mathematics.

Abstract: A data processing system having a mathematically consistent condition code architecture is disclosed for implementing single instruction range checking and limiting operations. The data processing system includes condition code flags that are set to provide indications of the occurrence of arithmetic overflow and the direction of the arithmetic overflow for all of the possible arithmetic operations that can be performed by an arithmetic logic unit within the digital processing system. Based upon the indicated occurrence of arithmetic overflow and the direction of the overflow, the numeric value of a software variable generated by one of the arithmetic operations is limited to an appropriate upper or lower bound of a predetermined range of acceptable values, if the numeric value was generated with the occurrence of arithmetic overflow, or the numeric value was generated without the occurrence of overflow, but was outside of the acceptable range of values.

Abstract: Interval arithmetic provides a convenient method for computing with ranges of reaJ numbers. Using interval arithmetic it is possible to produce an interval that can be verified to cent ain the exact solution. In some cases, we will show, that it is possible to recover the exact solution from the resulting interval approximation. For example, exact computation with real algebraic numbers can sometimes, be accomplished using interval arithmetic. The idea is to replace algebraic numbers with sufficiently small intervals containing them and perform algebraic number arithmetic usilng interval arithmetic. The resulting intervals will contain the desired algebraic numbers and can provide useful information concerning them. Interval approximations can be used to compute sign information, prove inequality, and using root separation theorems show equality. The major benefit of using interval arithmetic instead of algorithms for exact algebraic number computation is a substantial reduction in computing time. In this paper we summarize preliminary work on the use of interval arithmetic in real algebraic number comput ati on. We present algorithms for sign computation, bound computation, polynomial root bound computation, and polynomial real root isolation. If a polynomial with real algebraic number coefficients is replaced with a polynomial whose coefficients are intervals containing the algebraic numbers, it may be possible, using interval arithmetic, to isolate the real roots of the exact polynomial contained in the approximating interval polynomial. The major contribution of this paper is the presentation and study of an interval version of the coefficient sign variation method for real root isolation [AC76, CJ89, Joh91]. All of the algorithms described in this paper have been implemented using exact binary rational interval arithmetic (for a complete discussion of the algorithms and their implement ation see [Joh91]). The benefit of using exact intervzd arithmetic is that rounding is not necessary and that problems due to limited machine precision are never encoun-

Abstract: A method of transforming systolic arrays using bit-parallel arithmetic into arrays using digit-serial arithmetic is described. Digit-serial computation is an area-time efficient method of doing high-speed arithmetic calculations, having the advantage through appropriate choice of digit and word size of allowing throughput capacity to be matched to design needs. For a certain class of systolic arrays, digit-serial arithmetic allows a further very significant benefit by transforming arrays in which processors are under-utilized into arrays late with 100% processor utilization. >

Abstract: An ultra-high-performance VLSI image processor based on a multivalued residue arithmetic circuit is proposed for robot vision. Data communication between the mod m/sub i/ arithmetic units is not necessary in the residue arithmetic system, so that multiple mod m/sub i/ arithmetic units can be on different chips. Therefore, a number of mod m/sub i/ multiplier adders can be implemented on a single VLSI chip based on the modulus-slice concept. Each mod m/sub i/ arithmetic unit can be effectively implemented in parallel using the concept of pseudoprimitive root and multivalued current-mode circuit technology. Thus, the use of parallelism throughout makes the performance very high in comparison with the ordinary binary implementation. >

Abstract: We show that the following relationships hold: where the inclusions are strict.

Abstract: High-speed arithmetic algorithms based on redundant number representations with the digit set (0,1,2) in radix 2 are presented. The algorithms are suitable for implementing high-speed compact arithmetic in VLSI with multivalued logic circuits. Addition and subtraction can be performed in a constant time independent of the operand length. Internal n-digit multiplication and division using the redundant number representations can be performed in a time proportional to log/sub 2/ n and n, respectively. The circuits offer higher speed and greater compactness compared with the signed-digit arithmetic, since the basic addition cell has simpler scheme. The addition cell also has sufficient immunity to the supply voltage fluctuation and relatively low power dissipation. >

Abstract: PURPOSE:To inexpensively provide the matrix arithmetic processor which can execute an arithmetic processing of a determinant at a high speed by a simple structure. CONSTITUTION:The matrix arithmetic processor is provided with plural registers 1-12, 50-52 for storing each element of a determinant, arithmetic elements 21-46 provided by the number required for executing independently each operation in LU decomposition, and plural connecting lines for connecting each register and each arithmetic element, and each mutual arithmetic element along a flow of the operation by a prescribed rule, and each element stored in each register is calculated by each arithmetic element, and a result of its operation is held temporarily by an output part of each arithmetic element, on the connecting line or by an input part of each arithmetic element, and used for an operation executed by the next arithmetic element, by which plural operations are advanced in parallel, and also, held until the result of operation is used for the next operation and a read/write processing is omitted, therefore, the determinant can be subjected to arithmetic processing at a high speed.

Abstract: A general design methodology for arithmetic operators in current mode multiple value logic is described. It is based on the interconnection of single output functions of one current, quantizers, through summing nodes and current replicator circuits. Some quantizers are known already: radix 4 sum and carry circuits. The authors present new circuits for the discrete pseudologarithm and antilogarithm, which together give a single digit multiply circuit. These form a complete set that allows any arithmetic circuit to be constructed. >

Abstract: The design of a VLSI arithmetic unit for the support of signal processing and neural network algorithms is discussed. The arithmetic unit is conceived to allow the execution of inner product operations maintaining the silicon area and development costs under reasonable limits, and allowing the parameterization of the design in a modular way. A serial-bit pipeline multiplier and a fixed-point number format have been successfully used. These aspects are justified by a study on the accuracy required when implementing certain signal processing and neural network algorithms, for which some numerical examples are given. A design of a whole chip incorporating such an arithmetic unit and the structure of the required control unit are outlined. >

Abstract: A floating-point arithmetic unit based on the CORDIC algorithm is described. It computes a wide range of arithmetic, trigonometric, and hyperbolic functions and achieves a normalized peak performancle off 220 MFLOPs. The unit is implemented in 1.6pm double-metal CMOS technology and packaged in a 280 pin PGA.

Abstract: A set of reliable floating-point arithmetic algorithms for Berger encoded operands is presented. Closed-form equations are derived for floating-point addition, subtraction, multiplication and division. Given the IEEE floating-point number standard, the redundancy requirements of the proposed scheme are 39.47% for addition/subtraction, 45.65% for multiplication, and 45.44% for division of single precision numbers. The scheme uses only 16.14% for addition/subtraction, 36.44% for multiplication and 36.02% for division of double-precision numbers. >

Abstract: One of the major subsystems of the central processor unit is the arithmetic logic unit (ALU) in which the binary operations of addition, subtraction, multiplication, and division are performed All arithmetic functions can be related to addition: subtraction is performed by adding complemented numbers, multiplication by some form of repeated addition, and division by repeated subtraction Thus in all these functions the basic arithmetic element is the binary adder Consequently, the ALU consists of a number of registers which contain the operands, intermediate and final results, a basic adder (working in pure binary or binary-coded decimal) and a control unit All these functions, including memory, can be obtained on a single LSI chip

Abstract: It is known that a recursive least-square (RLS) algorithm with UD factorization equivalent to the (standard) RLS algorithm can be realized by using the systolic array proposed by Kung In general, in constructing a special hardware, the wordlength of a processor is related to the arithmetic processing speed and the area of the hardware Therefore, an important subject is how to shorten the wordlength of processors used in the systolic array executing the RLS method with UD factorization The authors have already carried out an operational error analysis in finite wordlength floating-point arithmetic and described that this algorithm can be executed with short arithmetic wordlength If the algorithm can be executed with short arithmetic wordlength also in the fixed-point arithmetic, then we can expect improved operational processing speed and simpler hardware structure compared to the special hardware of the floating-point arithmetic mode Thus, this paper describes an RLS method by finite wordlength fixed-point arithmetic with UD factorization and evaluates the operational error Then the evaluation of convergence values and number of updates of the algorithm are shown analytically Finally, the appropriateness of theoretical analysis results of convergence values and the number of updates are confirmed by computer simulations

Abstract: Compared to the complexity for realizing the prime factor discrete Fourier transform (DFT), the prime factor discrete Hartley transform requires some extra arithmetic operations for the realization of the prime factor mapping. These extra arithmetic operations can take up as much as 40% of the total arithmetic operations required. A new prime factor mapping scheme which requires no extra arithmetic operations is proposed for the computation of the discrete Hartley transform. It is achieved by embedding all the extra arithmetic operations into the subsequent short length computations, whereas the arithmetic complexities of these embedded short length modules remain unchanged. >

Abstract: A new system of arithmetic is presented called Dirichlet arithmetic which models the arithmetic on the coefficients of a Dirichlet series. This approach has the property that output digits depend on very few of the input digits for the basic operations of addition, multiplication, and division. What is perhaps more interesting is that Dirichlet arithmetic has the same near parallelism for all the elementary transcendental functions (log, exp, sin, cos, sinh, cosh, sin/sup -1/, cos/sup -1/, etc.) as well. Furthermore, this property follows from the fact that the values of the elementary transcendental functions are represented naturally by their Dirichlet digits and can be computed by operations on the input digits as simple as those for multiplication or division. >

Abstract: An arithmetic processor for a digital data processing system, and methods of operating same, employing a Truncated Dyadic Arithmetic (TDA) number representation for implementing exact equality testing of the results of rational arithmetic computations. The arithmetic processor includes circuitry for receiving a digital representation of a number, a register for storing the received number in a truncated dyadic arithmetic representation, including a mantissa field having m bits and an order field having o bits. A modulo field associated with each number is also stored or otherwise maintained. The arithmetic processor further includes circuitry for operating on the stored number in accordance with one or more arithmetic operations, including addition, subtraction, division, multiplication and square root, to obtain a result that is expressed in the truncated dyadic arithmetic representation. Additional circuitry compares the result to another result obtained from another truncated dyadic arithmetic operation.