Abstract: Sign/logarithm arithmetic is applicable to a variety of numerical applications where wide dynamic range and small wordsize are required. In this paper the basic sign/logarithm arithmetic operations required for signal processing (i.e., addition, subtraction, and multiplication) are reviewed, the computational errors are analyzed for FFT realization, and simulation results are presented which serve to verify the analysis. It is shown that the sign/logarithm approach provides improved arithmetic quantization error performance for a given word size over FFT's implemented with conventional fixed or floating point arithmetic, and that the sign/logarithm implementation is faster and less complex than conventional approaches.

Abstract: This paper describes the design of an arithmetic unit called CADAC (clean arithmetic with decimal base and controlled precision). Programming language specifications for carrying out "ideal" floating-point arithmetic are described first. These specifications include detailed requirements for dynamic precision control and exception handling, along with both complex and interval arithmetic at the level of a programming language such as Fortran or PL/I.

Abstract: An arithmetic system includes an arithmetic unit of a pipeline structure for executing arithmetic operations for instructions which require different arithmetic cycles. The arithmetic unit executes N arithmetics in pipeline for N instruction at maximum. Initiation of arithmetic operation for a new instruction in the arithmetic unit is indicated by an indicator which detects that each of the instruction executed in the arithmetic is N cycles before completion of the execution and allows arithmetic operation for the new instruction to be initiated in the succeeding cycle.

Abstract: In a floating-point arithmetic operation system performing an arithmetic operation on two given operands X, Y and providing the result Z of the arithmetic operation, the operands X and Y are each classified according to their attributes; and, at least part of the bits of the operand X, at least part of the bits of the operand Y or a predetermined set of bits are adopted as at least part of the result Z of the operation when the results of the classifications are one of predetermined combinations.

Abstract: Single-precision floatingpoint computations may yield an arbitrary false result due to cancellation and rounding errors. This is true even for very simple, structured arithmetic expressions such as Horner's scheme for polynomial evaluation. A simple procedure will be presented for fast calculation of the value of an arithmetic expression to least significant bit accuracy in single precision computation. For this purpose in addition to the floating-point arithmetic only a precise scalar product (cf. [2]) is required. If the initial floatingpoint approximation is not too bad, the computing time of the new algorithm is approximately the same as for usual floating-point computation. If not, the essential progress of the presented algorithm is that the inaccurate approximation is recognized and corrected. The algorithm achieves high accuracy, i.e. between the left and the right bound of the result there is at most one more floating-point number. A rigorous estimation of all rounding errors introduced by floating-point arithmetic is given for general triangular linear systems. The theorem is applied to the evaluation of arithmetic expressions.

Abstract: This paper extends the result of earlier work on the application of arithmetic codes to the constrained channel problem. We specifically present a general length-based fixed rate implementation technique which performs the arithmetic coding recursions during each channel time unit. This technique is superior to an earlier unpublished code for general constrained channels. The approach permits the design of codes for sophisticated channel constraints.

Abstract: This lecture begins with a brief account of recent work on unrestricted algorithms for computing mathematical functions, especially the development of error analysis based on a nontraditional definition of relative error. The main part of the talk describes the application of this analysis to real and complex arithmetic, and concludes with some new extensions that have been made in complex arithmetic.

Abstract: We present the results of a computational evaluation of two constraint aggregation approaches for solving integer linear programs. In some applications, particularly set partitioning problems, the schemes can aggregate significantly different number of constraints. We first discuss the implementation of these approaches using both single and multiple precision arithmetic. From these results, we empirically show that, in practical implementation and evaluation of an aggregation scheme, the degree of difficulty encountered in solving the resulting equality constrained knapsack problem is crucial. We conclude, as contrasted with the optimism expressed in some published works, that the aggregation approach has limited value for solving general integer linear programs, but may be useful in developing a heuristic algorithm for the set partitioning problem.

Abstract: Publisher Summary This chapter presents the evaluation of arithmetic expressions with maximum accuracy This algorithm uses floating-point operations with directed roundings and a scalar product of maximum accuracy in addition to the usual floating-point operations The computing time of the new algorithm is of the same order as for conventional floating-point calculation, assuming the latter does not fail completely In this case, additional computing time and storage are needed The method for polynomials is directly applicable to certain arithmetic expressions Any arithmetic expression can be transformed into a quotient in which the numerator and the denominator yield simultaneous linear equations These can be evaluated with maximum accuracy The final division causes a relative error of less than ɛ The last digit of the mantissa may then be incorrect This can be prevented if, for both the numerator and the denominator, a higher precision is simulated by representing the value as the sum of a floating-point number and an interval

Abstract: It is shown that floating point (or integer) multiplication can be reduced to the evalution of a very large class of functions including most of the nontrivial functions used in practice. That means that whenever any such function can be evaluated by boolean circuits of size S(n), then multiplication can be done with circuits of size O(S(n)). as well.

Abstract: The LSI Products Division of TRW is currently developing a third chip for its growing family of 22-bit floating point arithmetic devices. Joining the adder and the multiplier later this year will be the registered arithmetic logic unit (RALU), built in TRW's dual-metal one-micron bipolar "Omicron-B" process. Operating at a guaranteed (military temperature and supply voltage ranges) speed of 6 MHz, this device will be able to store, retrieve, add, subtract, and normalize 22-bit floating point numbers, convert between 22-bit floating point and 16-bit fixed point formats, and add, subtract, and perform logical operations on 16-bit fixed point numbers. With its built-in shifters and controls, it can also perform a fixed point multiplication or division or a floating point division in 16 clock cycles. The architecture of the RALU is very similar to that of the widely used 2901 four-bit microprocessor slice. The bus widths have been widened from 4 to 22 bits and the instruction set has been expanded to encompass the eight standard 2901 functions (for fixed point) and eight additional floating point and fixed-float conversion operations. The 2901's internal dual port RAM has been retained and widened for a 22-bit word size.

Abstract: For numerical applications a mathematically well founded computer arithmetic is necessary. In addition to the usual floating-point operations this arithmetic must also take into consideration the higher structures built upon these, e.g., complex numbers, intervals, matrices and vectors. In all cases the operations for these structures are deduced by a uniform construction principle, namely, semimorphism [6], by means of which mathematical structure is preserved as much as possible. This also results in optimal accuracy. For the implementation of the arithmetic many operations must be provided. This can be achieved only when the arithmetic as a whole is built up by a modular concept. The scalar product for any collection of floating-point numbers is introduced as an elementary operation. By means of these operations, all others in the higher spaces can be constructed in such a way that the requirement of semimorphism is also realized. The whole arithmetic is imbedded in a higher programming language and both are fully implemented on a microcomputer.

Abstract: : The simulation studies described show that sign-logarithm arithmetic can be implemented in a practical digital fast fourier transforms (FFT) analyser. Sign-logarithm arithmetic allows a smaller wordlength than conventional fixed point arithmetic whilst maintaining performance. Discussion of the hardware implementation of such a sign-logarithm FFT shows that power consumption can be less than conventional methods using bipolar multipliers. The use of a smaller wordlength allows a significant simplification of the system into which the FFT is placed and a higher data throughput rate. (Author)

Abstract: A number theoretic transform (NTT) is proposed, which can efficiently be computed by using ternary modular arithmetic. The new NTT relaxes the restriction imposed on the convolution length and, as in other efficient NTT's, its computation can be performed by means of data shifts and additions. A hardware implementation of the new NTT is then described and is compared with the implementation of conventional NTT's based on binary modular arithmetic.

Abstract: A data processing apparatus includes a CPU, a memory, and logic operation hardware. When a predetermined instruction code is identified, the logic operation hardware executes an arithmetic operation using data stored in the memory, while the CPU processes the same data. The logic operation hardware then writes the result of the arithmetic operation instead of the data processed by the CPU.

Abstract: PURPOSE: To attain the pipeline processing which can be reconstructed by connecting plural arithmetic modules to a common data bus line and applying the bus cycle with time division, and allotting the result to each arithmetic module. CONSTITUTION: The picture data is stored in a disk memory 1, and a host computer 2 actuates each of basic arithmetic modules 4 1 , 4 2 ... by a program for overall use of a picture processor 3. Each of these arithmetic modules has an independent picture processing function and is connected to a common bus line 6. The data and instructions are transferred from the computer 2, and an interruption is applied to a microcomputer 7. The input/output timing of each arithmetic module (e.g., modules 4 1 W4 4 ) is set to perform the pipeline processing. COPYRIGHT: (C)1984,JPO&Japio

Abstract: Three forms of interval floating-point arithmetic are defined in terms of absolute precision, relative precision, and combined absolute and relative precision. The absolute-precision form corresponds to the centered form of conventional rounded-interval arithmetic. The three forms are compared on the basis of the number of floating-point operations needed to generate error bounds for inner-product accumulation.

Abstract: A new design method for compact residue arithmetic circuit using multiple-valued charge-coupled devices (CCDS) is proposed The multiple-valued ring counter for the residue arithmetic is designed by using the CCDS Because the the structure of the counter is very simple, it is effectively used as the basic component to construct the residue arithmetic circuit Modulo-m addition is performed by shifting the modulo-m multiple-valued ring counter, and coefficient multiplication is done by converting the multiple-valued code between the counters The most important advantages of the proposed adder and multiplier are compact hardware and uniform operating time, so that these arithmetic circuits can be effectively employed in pipelining digital signal processing systems Finally, it is demonstrated that the hardware complexity of the digital filter constructed with the quaternary logic ccds can be reduced to 70percent of that of the corresponding binary implementation 13 references

Abstract: The paper proposes a new approach to the problem of summation of arithmetic functions which is more general than previous points of view.Bibliography: 15 titles.

Abstract: Major computer arithmetic systems are based on the concept of realizing only terminate rationals in positional notation. This paper proposes a new arithmetic scheme of indicating periodicity in the radix representation of a mantissa to realize recurring rationals as well as terminate rationals. A new arithmetic system adopting the scheme, called the “FLP/R* arithmetic system”, is proposed. Properties of the FLP/R* numbers and the procedure of the FLP/R* arithmetic are described.

Abstract: SINCE the inception of electronic computers, much effort has been directed towards the search of faster arithmetic techniques. For all scientific computations, the arithmetic units have always been considered as the heart of a digital computer. In the earlier approaches, emphasis on the arithmetic elements was limited to integer arithmetic with limited precision, as the cost of discrete components was the main driving factor. Circuit optimization with reduced components and techniques for high-speed arithmetic were crucial at that time. Later, software techniques were employed to include floating-point representation and to achieve desirable precision. The advances in LSI technology and the inception of microcomputers caused a-great deal of impact on the ways people used to think. Emphasis on circuit component reduction was shifted to iterative logic and minimization of chip types. This led to various uniformly structured and specialized units like cellular arrays, etc. Now, several high-speed multipliers and FFT processors are commercially available. The on-line processing requirement also enhanced acceptance of techniques like overlapping and pipelining. The error analysis has always been a lively topic of interest and so also the variable word-lengths. Parallel processing requirements led to the introduction of bit-slice ALU's. The current trend is to use high-speed arithmetic for various transforms and signal processing applications. This was clearly reflected from the papers submitted for the special issue.

Abstract: This article describes some of the methods and algorithms used in an implementation of floating point arithmetic following (almost) the IEEE standard defined in (1) The description is more directly algorithm-oriented than the ‘Implementation Guide’ for this standard (2), since the latter does not treat an actual implementation

Abstract: The ELXSI System 6400 is a new 64-bit general-purpose mainframe computer [1]. This paper decribes its arithmetic instruction set architecture and the organization of the arithmetic processor. The ELXSI instruction set supports a complete implementation of the proposed IEEE floating point standard [2], plus integer and decimal arithmetic. The System 6400 arithmetic processor uses ECL gate arrays to execute these instructions at high speed using a single board of hardware.

Abstract: Wetherell recently described an algebra of error values that could be added to the ordinary arithmetic of a programming language. Along with ordinary arithmetic values, error values were included in the set of computational quantities. The error values could participate in all arithmetic operations and return meaningful results. Unfortunately, the definitions of the error values were not precise enough. Using Brown's model of computer arithmetic, we supply precise definitions for the error values, define the fundamental arithmetic operations on the new values, comment on their properties, and discuss briefly how they might be used and implemented. We also compare our model to the error handling features of the proposed IEEE floating point standard.

Abstract: This paper describes aspects of an arithmetic design system (ADS) to support the quantitative evaluation of alternate number systems with respect to a given application and realization technology. In computer arithmetic we are concerned with establishing a correspondence between abstract quantities (numbers) and some physical representation (symbols), and with simulating the operations on these symbols. The ADS is intended to help study the cost and performance of alternate simulations. A finite number system is a triple consisting of a symbol set (elements are called "digit-vectors"), an interpretation set, a mapping between these two sets, and a set of operators (digit-vector algorithms) defined on its symbol set. A set of these digit vector algorithms are proposed for conducting arithmetic design. A number system matrix defines the digit vector algorithm for numerous number systems and a method for computing time and space complexity of compositions of these algorithms is proposed. An example of how the system could be used to compare addition, with and without out-of-range detection, for three number systems is given.

Abstract: An algorithm is described that seeks out Schrodinger eigenvalues Enl for a given central potential V(r). The algorithm has, in principle, arbitrary precision. A particular implementation has absolute error mod E-Enl mod decreasing as T-3, where T is machine computing time. The method is tested on the central Gaussian potential V(r)=-A exp(- lambda r2) of recent interest.