TL;DR: In this paper, a digital computer central processing unit is disclosed having an arithmetic unit which forms an element of an instruction processing pipeline, and the arithmetic unit has within it a plurality of arithmetic subunits each with its own storage and partitioned on a functional basis for the simultaneous execution of a pluralityof arithmetic steps within the arithmetic units while a plurality-of- instructions are simultaneously processed in their flow to the assembly.
Abstract: A digital computer central processing unit is disclosed having an arithmetic unit which forms an element of an instruction processing pipeline. The arithmetic unit has within it a plurality of arithmetic subunits each with its own storage and partitioned on a functional basis for the simultaneous execution of a plurality of arithmetic steps within the arithmetic unit while a plurality of instructions are simultaneously processed in their flow to the arithmetic unit. The sections of the arithmetic unit are accessible to operand input channels, the arithmetic unit further being partitioned for simultaneous single length operand execution or for double length operand execution.
TL;DR: Two algorithms are presented in the form of Fortran subroutines that computes the radix and number of digits of the floating-point numbers and whether rounding or chopping is done by the machine on which it is run.
Abstract: Two algorithms are presented in the form of Fortran subroutines. Each subroutine computes the radix and number of digits of the floating-point numbers and whether rounding or chopping is done by the machine on which it is run. The methods are shown to work on any “reasonable” floating-point computer.
TL;DR: This chapter is intended to summarize the most important results which have been obtained in the theory of coding for the correction and detection of errors in computer arithmetic.
Abstract: This chapter is intended to summarize the most important results which have been obtained in the theory of coding for the correction and detection of errors in computer arithmetic. The rapid growth in the size and speed of digital computers has placed stringent reliability demands on the arithmetic unit. Attempts to satisfy these demands have generally followed one of three directions: (1) Attempts to improve the reliability of the components used in the construction of the arithmetic unit, (2) attempts to improve reliability by incorporating hardware redundancy so that the result of a computation is unaffected by the failure of one or more of the replicated units which form the arithmetic unit, or so that the failure of one or more of the replicated units can be detected and the faulty units replaced, and (3) attempts to incorporate redundancy into the numbers themselves which are being processed so that erroneous results can be corrected or detected. This third approach, which is the subject of this chapter, tacitly assumes that it is possible to build the “decoder” which corrects or detects erroneous results much more reliably than the arithmetic unit which it monitors, so that the decoder can be considered error-free for practical purposes.
TL;DR: In this paper, algorithms for the four binary arithmetic operations and for rounding are presented, together with proofs of their correctness; appropriate formulas for a priori error analysis of these algorithms are presented.
Abstract: In this paper we discuss directed roundings and indicate how hardware might be designed to produce proper upward-directed, downward-directed, and certain commonly used symmetric roundings. Algorithms for the four binary arithmetic operations and for rounding are presented, together with proofs of their correctness; appropriate formulas for a priori error analysis of these algorithms are presented. Some of the basic applications of directed roundings are surveyed.
TL;DR: An automatic error analysis technique is given for determining, directly from the results of a trial low-precision interval arithmetic calculation, just how much precision and data accuracy are required to achieve a desired final accuracy.
Abstract: The problem considered is that of evaluating a rational expression to within any desired tolerance on a computer which performs variable-precision floating-point arithmetic operations. For example, the expression might be p/(p + 1/2 - e) √2), which is rational in the data p, e, √2. An automatic error analysis technique is given for determining, directly from the results of a trial low-precision interval arithmetic calculation, just how much precision and data accuracy are required to achieve a desired final accuracy. The techniques given generalize easily to the evaluation of many nonrational expressions.
TL;DR: A modular error detector for an adder of the type which provides both arithmetic and logical functions and incorporates carry-look-ahead addition is described in this article, which includes parity prediction of logical and arithmetic terms together with partial duplication.
Abstract: A modular error detector for an adder of the type which provides both arithmetic and logical functions and incorporates carrylook-ahead addition is described The error detector includes parity prediction of logical and arithmetic terms together with partial duplication Error checking of four bit arithmetic/logic modules is integrated with error checking of the carry-look-ahead unit Also, check parity generation and testing of the operands is integrated with the parity prediction
TL;DR: In this paper, two integrated circuit read-only-memory packages are interconnected with flip-flops and gates to form an arithmetic logic unit for performing arithmetic and logic operations in either a one-bit serial binary mode or a four-bit parallel binary-coded-decimal mode.
Abstract: Two integrated circuit read-only-memory packages are interconnected with flip-flops and gates to form an arithmetic logic unit for performing arithmetic and logic operations in either a one-bit serial binary mode or a four-bit parallel binary-coded-decimal mode.
TL;DR: It is shown that the computing time for adding and taking the derivative of rational functions is 2 orders of magnitude faster using the modular algorithms.
Abstract: Despite recent advances in speeding up many arithmetic and algebraic algorithms plus a general increase in algorithm analyses, no computing time study has ever been done for algorithms which perform the rational function arithmetic operations. Mathematical symbol manipulation systems which provide for operations on rational functions use algorithms which were initially given by P. Henrici in 1956. In this paper, these algorithms are precisely specified and their computing times analyzed. Then, new algorithms based on the use of modular arithmetic are developed and analyzed. It is shown that the computing time for adding and taking the derivative of rational functions is 2 orders of magnitude faster using the modular algorithms. Also, the computing time for rational function multiplication will be one order of magnitude faster using the modular algorithm.
TL;DR: The chapter describes a self-contained finite precision rational arithmetic system where results, which overflow, are not simply aborted out to a floating-point representation or to an overflow message indicator.
Abstract: Publisher Summary This chapter discusses number theoretic foundations of finite precision arithmetic. The process of radix conversion from one finite precision number system to another can be denoted by a restricted mapping. The chapter describes a few properties of such restricted mappings and highlights the practical numeric problems encountered in software implementations of programming languages, which allow mixed arithmetic between differently based floating-point data. It describes a self-contained finite precision rational arithmetic system where results, which overflow, are not simply aborted out to a floating-point representation or to an overflow message indicator. The chapter highlights a few recent number theoretic results in the area of finite precision number systems.
TL;DR: A new multiplier is developed which has an array structure compatible with one of the dividers, and it is shown how this multiplier/divider can be implemented using Hoffmann cells, requiring considerably fewer cells than two separate units.
Abstract: A number of papers have been written recently describing cellular-array multipliers and dividers. The usefulness of these schemes is in their speed of operation and the simplicity of the array structures. However, the structures are such that multiplication and division require separate arrays and possibly different types of cells. Since the number of cells in an array is proportional to the square of the word length used, it would be a tremendous saving if the multiplier and divider could share a large percentage of the hardware. In this paper, some of the existing multiplier and divider arrays are briefly described, and a new multiplier is developed which has an array structure compatible with one of the dividers. It is then shown how this multiplier/divider can be implemented using Hoffmann cells, requiring considerably fewer cells than two separate units. With the addition of a few more control lines, the array can be operated as a complete arithmetic unit allowing a range of single-precision arithmetic and logical operations and double-precision arithmetic operations.
TL;DR: It is shown that the modular arithmetic weight of an integer is invariant to the cyclic shifts of its radix-2 form, which leads to a reduced search for the minimum weight codeword in a cyclic AN-code as well as to a better understanding of previous work.
Abstract: This note shows that the modular arithmetic weight of an integer is invariant to the cyclic shifts of its radix-2 form. This result leads to a reduced search for the minimum weight codeword in a cyclic AN-code as well as to a better understanding of previous work.
TL;DR: In this Department the Monthly presents easily stated research problems dealing with notions ordinarily encountered in undergraduate mathematics.
Abstract: In this Department the Monthly presents easily stated research problems dealing with notions ordinarily encountered in undergraduate mathematics. Each problem should be accompanied by relevant references (if any are known to the author) and by a brief description of known partial results. Manuscripts should be sent to Richard Guy, Department of Mathematics, Statistics, and Computing Science, The University of Calgary, Calgary 44, Alberta, Canada.