Application-specific instruction-set processor

Abstract: A processor is described which can achieve highly parallel execution of programs represented in data-flow form. The language implemented incorporates conditional and iteration mechanisms, and the processor is a step toward a practical data-flow processor for a Fortran-level data-flow language. The processor has a unique architecture which avoids the problems of processor switching and memory/processor interconnecion that usually limit the degree of realizable concurrent processing. The architecture offers an unusual solution to the problem of structuring and managing a two-level memory system.

Abstract: A process of operating a computer system ( 100 ). The computer system ( 100 ) has a storage (HDD, 110 ) holding an operating system (OS) and an application program (APP.exe), a first processor ( 106 ) having an instruction set, and a second processor ( 1730 ) having a different instruction set. The process includes steps of 1) running ( 2424 ) at least some of the operating system (OS) on the first processor ( 106 ) so that the first processor ( 106 ) sets up for at least part of the application program at run time at least one second processor object (VSP OBJECT 1 ); and 2) concurrently running the second processor ( 3310 ) to access the second processor object (VSP OBJECT 1 ) and thereby determine operations for the second processor ( 1730 ) to access second processor instructions for said part of the application program (APP.exe) and data to be processed according to said second processor instructions, and running ( 2436 ) the second processor ( 1730 ) to process the data according to said second processor instructions. Other processes, systems, devices and methods are also disclosed.

Abstract: A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single processor and instruction set. Advantageously, the embedded logic on the DRAM chip implements the memory intensive processing tasks, thus reducing the amount of traffic that needs to be bussed back and forth between the CPU core and the embedded DRAM chips. The embedded DRAM logic monitors and manipulates the instruction stream into the CPU core. The architecture of the instruction set, data paths, addressing, control, caching, and interfaces are developed to allow the system to operate using a standard programming model. Specialized video and graphics processing systems are developed. Also, an extended very long instruction word (VLIW) architecture implemented as a primary VLIW processor coupled to an embedded DRAM VLIW extension processor efficiently deals with memory intensive tasks. In different embodiments, standard software can be accelerated either with or without the express knowledge of the processor.

Abstract: Methods and systems are provided for enabling a network between a first and a second processor using at least one additional processor separate from the first and second processors. In one embodiment, the first processor and the second processor may each be independently administered through the additional processor. Further, the additional processor may receive information indicating a consent on behalf of the first processor to enabling a tunnel between the first processor and the second processor and receives information indicating a consent on behalf of the second processor to enabling a tunnel between the second processor and the first processor. The additional processor may determine a first virtual address for the first processor and a second virtual address for the second processor such that the first and second virtual addresses uniquely identify the first and second processors, respectively, and are routable through the network. The additional processor may provide to each of the first and second processors the first and second virtual addresses to enable one or more tunnels between the first and the second processors.