Abstract: Passive physical attacks, like power analysis, pose a serious threat to the security of digital circuits. In this work, we introduce an efficient side-channel protected Advanced Encryption Standard (AES) hardware design that is completely scalable in terms of protection order. Therefore, we revisit the private circuits scheme of Ishai et al. [13] which is known to be vulnerable to glitches. We demonstrate how to achieve resistance against multivariate higher-order attacks in the presence of glitches for the same randomness cost as the private circuits scheme. Although our AES design is scalable, it is smaller, faster, and less randomness demanding than other side-channel protected AES implementations. Our first-order secure AES design, for example, requires only 18 bits of randomness per S-box operation and 6 kGE of chip area. We demonstrate the flexibility of our AES implementation by synthesizing it up to the 15\(^{\text {th}}\) protection order.

Abstract: A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.

Abstract: The importance of cryptography on ensuring security or integrity of the electronic data transaction had become higher during the past few years. Multiple security protocols are currently using various block ciphers. One of the most widely used block ciphers is the Advanced Encryption Standard (AES) which is chosen as a standard for its higher efficiency and stronger security than its competitors. Unfortunately, the encryption and decryption processes of AES takes a considerable amount of time for large data size. The GPU is an attractive platform for accelerating block ciphers and other cryptography algorithms due to its massively parallel processing power. In this work, an implementation of the AES-128 ECB Encryption on three different GPU architectures (Kepler, Maxwell and Pascal) has been presented. The results show that encryption speeds with 207 Gbps on the NVIDIA GTX TITAN X (Maxwell) and 280 Gbps on the NVIDIA GTX 1080 (Pascal) have been achieved by performing new optimization techniques using 32bytes/thread granularity.

Abstract: Cryptography is the science of secure data transmission through an insecure channel. Advanced Encryption Standard (AES) is the most widely and secure symmetric key cryptographic algorithm today. The complexity of AES is dominated by the substitution box (S-box) transformation which is considered as one of the most complicated and costly part of the system because it is the only non-linear structure. In this article, we present high speed efficient AES architecture. We have used pipeline technique to allow a parallel processing in order to obtain high throughput. In addition, 5-stage pipeline S-box design using combinational logic is introduced to increase the speed and the maximum operating frequency. Furthermore, pipeline registers are inserted in optimal placements to reduce the occupied area and reach an efficient architecture. The proposed design had been successfully implemented in virtex-6 FPGA device using Xilinx ISE 14.7. It achieves a throughput of 79Gbps and occupied 4830 slices memory.

Abstract: While the AES algorithm is regarded as secure, many implementations of AES are prone to cache side-channel attacks. The lookup tables traditionally used in AES implementations for storing precomputed results provide speedup for encryption and decryption. How such lookup tables are used is known to affect the vulnerability to side channels, but the concrete effects in actual AES implementations are not yet sufficiently well understood. In this article, we analyze and compare multiple off-the-shelf AES implementations wrt. their vulnerability to cache side-channel attacks. By applying quantitative program analysis techniques in a systematic fashion, we shed light on the influence of implementation techniques for AES on cache-side-channel leakage bounds.

Abstract: There is a great research in the field of data security these days. Storing information digitally in the cloud and transferring it over the internet proposes risks of disclosure and unauthorized access; thus, users, organizations, and businesses are adapting new technology and methods to protect their data from breaches. In this paper, we introduce a method to provide higher security for data transferred over the internet, or information based in the cloud. The introduced method, for the most part, depends on the Advanced Encryption Standard (AES) algorithm, which is currently the standard for secret key encryption. A standardized version of the algorithm was used by The Federal Information Processing Standard 197 called Rijndael for the AES. The AES algorithm processes data through a combination of exclusive-OR operations (XOR), octet substitution with an S-box, row and column rotations, and MixColumn operations. The fact that the algorithm could be easily implemented and run on a regular computer in a reasonable amount of time made it highly favorable and successful. In this paper, the proposed method provides a new dimension of security to the AES algorithm by securing the key itself such that even when the key is disclosed; the text cannot be deciphered. This is done by enciphering the key using Output Feedback Block Mode Operation. This introduces a new level of security to the key in a way, in which deciphering the data requires prior knowledge of the key and the algorithm used to encipher the key for the purpose of deciphering the transferred text.

Abstract: The Advanced Encryption Standard(AES) is used in security areas widely now. However, there is still a large room for further improvement of its execution efficiency. Since the graphics processing unit(GPU) with potent ability of parallel computing has been applied in general purpose of computation, people have tried to use it to faster execution time in various cryptographic algorithms. This paper discusses how the performance of CBCAES decryption based on GPU is influenced by 4 key parameters that include the size of input data, the number of threads per block, memory allocation style and parallel granularity. Further more, we compare the performance of AES on GPU to that of standard AES, AES-NI and find that when the size of input data is different, the implementations with different parameters setting achieve the best performance. So we provide several advices about how to implement CBC-AES on GPU aiming at different size of input data. In particular, our best performance of experiments on GPU(NVIDIA Tesla K40m) is about 112 times faster than the implementation of AES on CPU (Intel Xeon E5-2650) by using our optimization method.

Abstract: In this paper, we investigate the efficiency of FPGA implementations of AES and AES-like ciphers, specially in the context of authenticated encryption. We consider the encryption/decryption and the authentication/verification structures of OCB-like modes (like OTR or SCT modes). Their main advantage is that they are fully parallelisable. While this feature has already been used to increase the throughput/performance of hardware implementations, it is usually overlooked while comparing different ciphers. We show how to use it with zero area overhead, leading to a very significant efficiency gain. Additionally, we show that using FPGA technology mapping instead of logic optimization, the area of both the linear and non linear parts of the round function of several AES-like primitives can be reduced, without affecting the run-time performance. We provide the implementation results of two multi-stream implementations of both the LED and AES block ciphers. The AES implementation in this paper achieves an efficiency of 38 Mbps/slice, which is the most efficient implementation in literature, to the best of our knowledge. For LED, achieves 2.5 Mbps/slice on Spartan 3 FPGA, which is 2.57x better than the previous implementation. Besides, we use our new techniques to optimize the FPGA implementation of the CAESAR candidate Deoxys-I in both the encryption only and encryption/decryption settings. Finally, we show that the efficiency gains of the proposed techniques extend to other technologies, such as ASIC, as well.

Abstract: The Advanced Encryption standard (AES) cryptosystem for the small scale network presents the implementation of the AES algorithm, FIPS 197, on the microcontroller operated on the real-time operating system (RTOS) for securing data in a small scale network for example as an UAVs wireless communication. The Electronic Code Book (ECB) mode of the AES algorithm is mainly used as the cryptographic core. The RTOS has a scheduler with Pre-emptive scheduling algorithm in which each role is to give access the processor for tasks with higher priority. The target hardware is implemented on the arm cortex-M4. The performances of the implemented system are evaluated based on the communication of UAVs including the control commands and telemetry commands.

Abstract: In cryptography, Advanced Encryption Algorithm (AES) is a computer security standard defined by National Institute of Standards & Technology (NIST). It is a symmetric key algorithm which uses block of 128 bits of input data & key with different sizes. The size of key can be 128,192 or 256 bits. This paper explains a hardware platform for implementation of AES algorithm with key size 128 bits. Field Programmable Gate Array (FPGA) Artix 7 Nexys 4 kit is used to perform the algorithm by configuring it with the help of Software Development Kit (SDK) in Xilinx ISE design suite. Microblaze is the soft core processor used for the interface between hardware & software. The data is transmitted to the FPGA with the help of MATLAB.

Abstract: Since the standardization of AES/Rijndael symmetric-key cipher by NIST in 2001, it gained widespread acceptance in various protocols and withstood intense scrutiny from the theoretical cryptanalysts. From the physical implementation point of view, however, AES remained vulnerable. Practical attacks on AES via fault injection, differential power analysis, scan-chain and cache-access timing have been demonstrated so far. In this paper, we propose a novel and effective attack, termed Trace Buffer Attack. Trace buffers are extensively used for post-silicon debug of integrated circuits. We identify the trace buffer as a source of information leakage. We first report the detailed process of trace buffer attack assuming that the register-transfer level (RTL) implementation is available. We further analyze the AES encryption algorithm and Rijndael’s key expansion algorithm, and illustrate that trace buffer attack is feasible without implementation (RTL) knowledge. Our experimental results show that trace buffer attack is capable of partially recovering the secret keys of different AES implementations.

Abstract: In recent years, academic focus on side chan-nel analysis has increased due to their effectiveness in leaking information from secure systems. Advanced Encryption Standard or Rinjdael has been the object of scrutiny ever since its inception as a federal standard. Presently, it is one of the most widely used encryption algorithms in the world and has withstood the various efforts to crypt-analyze it. With academic focus on time leaking code implementations increasing in the 90s, and successful crypt-analysis of many algorithms due to side channel data leakage and the fact that improper software implementations can leak information has brought focus on side channel analysis of AES. We shall try and implement the cache timing attack on a modern server and modern implementations and observe the results firsthand. In this paper, the authors try and implement cache timing attack on various AES implementations over modern processors. The practical importance of mounting an attack over a non-idealized system and analyzing these real world results can be considered the primary objectives of this paper.

Abstract: The Advanced Encryption Standard (AES) algorithm has been widely used to secure communication systems. However, the encryption algorithm is vulnerable to fault injection attacks and various attack methods have been studied. Some methods are just proposed in theory and have not been validated in practice. In this paper, we actualize a fault injection attack on an FPGA AES implementation. We propose a method to generate the highly accurate clock glitch to inject faults in the encryption process. We show that if the frequency of the clock glitch is carefully selected, only 6 faulty ciphertexts are necessary to discover the secret key.

Abstract: The Advanced Encryption Standard (AES) is One of the most popular symmetric block cipher because it has better efficiency and security The AES is computation intensive algorithm especially for massive transactions The Graphics Processing Unit (GPU) is an amazing platform for accelerating AES it has good parallel processing power Traditional approaches for implementing AES using GPU use 16 byte per thread as a default granularity In this paper, the AES-128 algorithm (ECB mode) is implemented on three different GPU architectures with different values of granularities (32,64 and 128 bytes/thread) Our results show that the throughput factor reaches 277 Gbps, 201 Gbps and 78 Gbps using the NVIDIA GTX 1080 (Pascal), the NVIDIA GTX TITAN X (Maxwell) and the GTX 780 (Kepler) GPU architectures

Abstract: Cryptography has an important role in data security against known attacks and decreases or limits the risks of hacking information, especially with rapid growth in communication techniques. In the recent years, we have noticed an increasing requirement to implement cryptographic algorithms in fast rising high-speed network applications. In this paper, we present high throughput efficient hardware implementations of Advanced Encryption Standard (AES) cryptographic algorithm. We have adopted pipeline technique in order to increase the speed and the maximum operating frequency. Therefore, registers are inserted in optimal placements. Furthermore, we have proposed 5-stage pipeline S-box design using combinational logic to reach further speed. In addition, efficient key expansion architecture suitable for our proposed design is also presented. In order to secure the hardware implementation against side-channel attacks, masked S-box is introduced. The implementations had been successfully done by virtex-6 (xc6vlx240t) Field-Programmable Gate Array (FPGA) device using Xilinx ISE 14.7. Our proposed unmasked and masked architectures are very fast, they achieve a throughput of 93.73 Gbps and 58.57 Gbps, respectively. The obtained results are competitive in comparison with the implementations reported in the literature.

Abstract: In this paper, we investigate the efficiency of FPGA implementations of AES and AES-like ciphers, specially in the context of authenticated encryption. We consider the encryption/decryption and the authentication/verification structures of OCB-like modes (like OTR or SCT modes). Their main advantage is that they are fully parallelisable. While this feature has already been used to increase the throughput/performance of hardware implementations, it is usually overlooked while comparing different ciphers. We show how to use it with zero area overhead, leading to a very significant efficiency gain. Additionally, we show that using FPGA technology mapping instead of logic optimization, the area of both the linear and non linear parts of the round function of several AES-like primitives can be reduced, without affecting the run-time performance. We provide the implementation results of two multi-stream implementations of both the LED and AES block ciphers. The AES implementation in this paper achieves an efficiency of 38 Mbps/slice, which is the most efficient implementation in literature, to the best of our knowledge. For LED, achieves 2.5 Mbps/slice on Spartan 3 FPGA, which is 2.57x better than the previous implementation. Besides, we use our new techniques to optimize the FPGA implementation of the CAESAR candidate Deoxys-I in both the encryption only and encryption/decryption settings. Finally, we show that the efficiency gains of the proposed techniques extend to other technologies, such as ASIC, as well.

Abstract: In this paper, a new compact implementation of S-Box based on composite field arithmetic (CFA) is proposed for block ciphers AES and SM4. Firstly, using CFA technology, the multiplicative inverse (MI) over GF(28) is mapped into GF((24)2) and the new architecture of S-Box is designed. Secondly, the MI over GF(24) is optimized by Genetic algorithm (GA), and the multiplication over GF(24) and the constant matrix multiplications are optimized by delay-aware common sub-expression elimination (DACSE) algorithm. Finally, compared with the direct implementation, the area reduction of MI over GF((24)2) and the new S-Box are up to 49.29% and 43.80%, severally. In 180 nm 1.8V COMS technology, compared to the synthesized results of AES S-Box and SM4 S-Box, the area and power consumption of the new S-Box are reduced by 24.76% and 38.54%, respectively.

Abstract: Although AES is designed to be secure against a wi de variety of linear and differential attacks, security ultimately depends on a combination of the engineering implementation and proper application by intended users. In this work, we attack a publicly -available VHDL implementation of AES by exploiting a partial result visible at the top-level public inte rface of the implementation. The vulnerability ren d rs the security of the implementation equivalent to a oneround version of AES. An algorithm is presented th at exploits this vulnerability to recover the secret k y in 231 operations. The algorithm is coded in an interpre ted high-level language and successfully recovers secre t keys, with one set of known plaintext, using a ge neralpurpose CPU in an average of 30 minutes.

Abstract: The growth of computer systems and electronic communications and transactions has meant that the need for effective security and reliability of data communication, processing and storage is more important than ever. In this context, cryptography is a high priority research area in engineering. The Advanced Encryption Standard (AES) is a symmetric-key criptographic algorithm for protecting sensitive information and is one of the most widely secure and used algorithm today. High-throughput, low power and compactness have always been topic of interest for implementing this type of algorithm. In this paper, we are interested on the development of high throughput architecture and implementation of AES algorithm, using the least amount of hardware possible. We have adopted a pipeline approach in order to reduce the critical path and achieve competitive performances in terms of throughput and efficiency. This approach is effectively tested on the AES S-Box substitution. The latter is a complex transformation and the key point to improve architecture performances. Considering the high delay and hardware required for this transformation, we proposed 7-stage pipelined S-box by using composite field in order to deal with the critical path and the occupied area resources. In addition, efficient AES key expansion architecture suitable for our proposed pipelined AES is presented. The implementation had been successfully done on Virtex-5 XC5VLX85 and Virtex-6 XC6VLX75T Field Programmable Gate Array (FPGA) devices using Xilinx ISE v14.7. Our AES design achieved a data encryption rate of 108.69 Gbps and used only 6361 slices ressource. Compared to the best previous work, this implementation improves data throughput by 5.6% and reduces the used slices to 77.69%.

Abstract: The Advanced Encryption Standard (AES) is a widely-used efficient cryptographic algorithm. Although AES is fast both in software and hardware, it is time-consuming to do data encryption especially for large amount of data. Therefore, it is a lasting effort to accelerate AES algorithms. This paper presents SW-AES, a parallel AES implementation on the Sunway TaihuLight, the fastest supercomputer in the world that takes the SW26010 many-core processor as the basic building block. According to the architectural features of SW26010, SW-AES exploits parallelism from different levels, including 1) inter-CPE (Compute-Processing Element) paral- lelism that distributes tasks among the 256 on-chip CPEs, 2) intra-CPE data parallelism enabled by the Single-Instruction Multiple-Data (SIMD) instructions inside each CPE, and 3) instruction-level parallelism that pipelines memory access and the computation. As a result, SW-AES can gain a maximum throughput of 13.49 GB/s on a single SW26010 node, which is 210.78 × higher than the latest parallel AES implementation on the Sunway TaihuLight, and about 37.3% higher than the latest AES implementation on the GTX 480 GPU.

Abstract: In the last decades, digital communications and network technologies have been growing rapidly, which makes secure speech communication an important issue. Regardless of the communication purposes, military, business or personal, people want a high level of security during their conversations. In this context, many voice encryption methods have been developed, which are based on cryptographic algorithms. One of the major issues regarding these algorithms is to identify those that can ensure high throughput when dealing with reduced bandwidth of the communication channel. A solution is to use resource constrained embedded systems because they are designed such that they consume little system resources, providing at the same time very good performances. To fulfil all the strict requirements, hardware and software optimizations should be performed by taking into consideration the complexity of the chosen algorithm, the mapping between the selected architecture and the cryptographic algorithm, the selected arithmetic unit (floating point or fixed point) and so on. The purpose of this paper is to compare and evaluate based on several criteria the Digital Signal Processor (DSP) implementations of three voice encryption algorithms in real time. The algorithms can be divided into two categories: asymmetric ciphers (NTRU and RSA) and symmetric ciphers (AES). The parameters taken into consideration for comparison between these ciphers are: encryption, decryption and delay time, complexity, packet lost and security level. All the previously mentioned algorithms were implemented on Blackfin and TMS320C6x processors. Making hardware and software level optimizations, we were able to reduce encryption/decryption/delay time, as well as to reduce the energy consumed. The purpose of this paper is to determine which is the best system hardware (DSP platform) and which encryption algorithm is feasible, safe and best suited for real-time voice encryption.

Abstract: Aggressive voltage scaling (AVS) technique is an efficient and lightweight countermeasure for cryptographic circuits against conventional first-order (CFO) differential power analysis (DPA) attacks. However, in this paper, it is demonstrated that AVS technique is vulnerable against bivariate first-order (BFO) DPA attacks since the noise inserted by the random scaling of the voltage can be filtered easily under BFO DPA attacks. To protect a cryptographic circuit that utilizes voltage scaling against BFO attacks, a lightweight implementation of the advanced encryption standard (AES) is proposed. In the proposed technique, even if the noise inserted by the random voltage scaling is filtered, a significant amount of random power noise can still be present in the side-channel leakage obtained by BFO DPA attacks. As demonstrated with the simulation results, when BFO DPA attacks are implemented on the proposed lightweight random AES engine with AVS technique, the measurement-to-disclose (MTD) value is enhanced over 1 million. Alternatively, the MTD value is less than 6,000 under BFO DPA attacks for a conventional AES engine with AVS technique.

Abstract: Objectives: To increase needed for exchanging digital photos electronically, due to alarming demand for multimedia applications, and because of the increasing use of images in electronic processes. Hence, the need for protection by unauthorized user is necessary. Method: This paper primarily is focusing on the necessary protection of these images using a specific analyzes algorithm: Advanced Encryption Standard (AES) with a full its description, which is known as an algorithm (Rijndael). Findings: It will be determined the address decryption, which is made up of different styles in all encryption and decryption steps in order to protect the valuable information. This algorithm will be implemented on MATLAB software programming. Application: The above results and analysis for this crypto system based on AES algorithm give a high performance. So we have reason to believe that use this method to encrypt the image will have a very good prospect in the future.

Abstract: Since the establishment of the Advanced Encryption Standard (AES), several industrial and academic contributions have been presented towards its improvement focusing on different requirements. The typical restrictions considered in the state of the art are speed, resource efficiency, and compactness. Within the several existing technologies, FPGAs have gained a big market share due to their high adaptability, decreasing cost, and ease to prototype and low time to market. Within FPGA technology, several variations of AES datapaths have been proposed since 2001, differentiating themselves in the datapath bit-width, pipeline staging, Key Scheduling approaches, and round rolling/unrolling. More dedicated solutions have also been proposed for each of the AES operations, considering the use of BRAMs and DSPs, allowing to improve the implementations alongside the inherent evolution of FPGA technologies. This chapter comprises and presents a comprehensive study of state of art AES implementations on FPGA, including a detailed presentation of the AES algorithm and a discussion of the most influential and the most recent architectures proposed to date, providing readers with an updated common ground for future research.

Abstract: The aim of this work is to describe three different architectural designs for AES cipher, which is a symmetric block encryption standard. The three architectures are oriented to different applications and are designed using different approaches, like pipeline structures and resource sharing. They also include an AMBA AHB interface, which is an open standard that defines the interconnection of blocks in a System-on-Chip (SoC).

Abstract: Side Channel Attacks are an important attack vector on secure AES implementations. The Correlation-Enhanced Power Analysis Collision Attack by Moradi et al. [MME10] is a powerful collision attack that exploits leakage caused by collisions in between S-Box computations of AES. The attack yields observations from which the AES key can be inferred. Due to noise, an insufficient number of collisions, or errors in the measurement setup, the attack does not find the correct AES key uniquely in practice, and it is unclear how to determine the key in such a scenario. Based on a theoretical analysis on how to quantify the remaining entropy, we derive a practical search algorithm. Both our theoretical analysis and practical experiments show that even in a setting with high noise or few available traces we can either successfully recover the full AES key or reduce its entropy significantly.