Abstract: Graphics Processing Units (GPUs) have been used to run a range of cryptographic algorithms. The main reason to choose a GPU is to accelerate the encryption/decryption speed. Since GPUs are mainly used for graphics rendering, and only recently have they become a fully-programmable parallel computing device, there has been little attention paid to their vulnerability to side-channel attacks. In this paper we present a study of side-channel vulnerability on a state-of-the-art graphics processor. To the best of our knowledge, this is the first work that attempts to extract the secret key of a block cipher implemented to run on a GPU. We present a side-channel power analysis methodology to extract all of the last round key bytes of a CUDA AES (Advanced Encryption Standard) implementation run on an NVIDIA TESLA GPU. We describe how we capture power traces and evaluate the power consumption of a GPU. We then construct an appropriate power model for the GPU. We propose effective methods to sample and process the GPU power traces so that we can recover the secret key of AES. Our results show that parallel computing hardware systems such as a GPU are highly vulnerable targets to power-based side-channel attacks, and need to be hardened against side-channel threats.

Abstract: In these days use of digital data exchange is increasing day by day in every field Information security plays very important role in storing and transmitting the data When we transmit a multimedia data such as audio, video, images etc over the network, cryptography provides security In cryptography, we encode data before sending it and decode it on receiving, for this purpose, we use many cryptographic algorithms AES and DES are most commonly used cryptographic algorithms AES provides the encryption to secure the data before the transmission and DES also provides security as AES In this paper we discussed AES and DES and their comparison using MATLAB software After applying AES and DES, we compare their result on the basis of avalanche effect, simulation time and memory required by AES and DES

Abstract: Lightweight encryption circuits are crucial to ensure adequate information security in emerging millimeter-scale platforms for the Internet of Things, which are required to deliver moderately high throughput under stringent area and energy budgets. This requires the adoption of specialized AES accelerators, as they offer orders of magnitude energy improvements over microcontroller-based implementations. In this paper, we present the architectural exploration of lightweight AES accelerators with the goal of minimizing the energy consumption. Also, the lower bound of the number of cycles per encryption in lightweight AES designs is estimated as a function of the number of available S-boxes. Combined with sub-/near-threshold circuit techniques, we present a low-cost ultra energy-efficient AES encryption core for cubic-millimeter platforms. Our test chip achieves high energy efficiency of 0.83 pJ/bit at 0.32V, which outperforms the state-of-the-art low-cost AES designs by 7×.

Abstract: Security mechanisms to protect our systems and data from malicious adversaries have become essential. Strong encryption algorithms are an important building block of these solutions. However, each application has its own requirements and it is not always possible to find a cipher that meets them all. This work compares unrolled combinational hardware implementations of six lightweight block ciphers, along with an AES implementation as a baseline. Up until now, the majority of such ciphers were designed for area-constrained environments where speed is often not crucial, but recently the need for single-cycle, low-latency block ciphers with limited area requirements has arisen to build security architectures for embedded systems. Our comparison shows that some designers are already on this track, but a lot of work still remains to be done.

Abstract: Currently, AES is regarded as the most popular symmetric cryptographic algorithm. It is very significant to develop high performance AES to further broaden its widespread applications. And in this paper, it is mainly about the different optimized designs and implementations of AES algorithm. Firstly, it tests the fast implementation of AES algorithm and the performance has been improved by about 50 times when compared to the standard AES algorithm, Secondly, using the Intel AES-NI extended instruction sets, and the performance has been improved by about 50 times compared with the fast implementation of AES algorithm, Finally, using CUDA and GPU to execute the AES in parallel, and it can improve the performance by about 18 times compared with the fast implementation of AES algorithm.

Abstract: An AES algorithm can beimplemented in software or hardware but hardware implementation is more suitable for high speed applications in real time. AES is most secure security algorithm to maintain safety and reliability of data transmission. The main goal of paper is AES hardware implementation to achieve less area and low power consumption which maintain standard throughput of data, also to achieve high speed data processing and reduce time for key generating. AES hardware implementation caneasily reset and immediately erase data on disk. The conventional Sboxcombinational logic is replaced by BRAM which gives instantaneous output. The AES 128/196/256 is implements on a FPGA using HDL language with help of Xilinx ISE tool.

Abstract: Securing cryptographic implementations against side-channel attacks is one of the most important challenges in modern cryptography. Many countermeasures have been introduced for this purpose, and analyzed in specialized security models. Formal solutions have also been proposed to extend the guarantees of provable security to physically observable devices. Masking and leakage-resilient cryptography are probably the most investigated and best understood representatives of these two approaches. Unfortunately, claims whether one, the other or their combination provides better security at lower cost remained vague so far. In this paper, we provide the first comprehensive treatment of this important problem. For this purpose, we analyze whether cryptographic implementations can be security-bounded, in the sense that the time complexity of the best side-channel attack is lower-bounded, independent of the number of measurements performed. Doing so, we first put forward a significant difference between stateful primitives such as leakage-resilient PRGs (that easily ensure bounded security), and stateless ones such as leakage-resilient PRFs (that hardly do). We then show that in practice, leakage-resilience alone provides the best security vs. performance tradeoff when bounded security is achievable, while masking alone is the solution of choice otherwise. That is, we highlight that one (x)or the other approach should be privileged, which contradicts the usual intuition that physical security is best obtained by combining countermeasures. Besides, our experimental results underline that despite defined in exactly the same way, the bounded leakage requirement in leakage-resilient PRGs and PRFs imply significantly different challenges for hardware designers. Namely, such a bounded leakage is much harder to guarantee for stateless primitives (like PRFs) than for statefull ones (like PRGs). As a result, constructions of leakage-resilient PRGs and PRFs proven under the same bounded leakage assumption, and instantiated with the same AES implementation, may lead to different practical security levels.

Abstract: The Advanced Encryption Standard (AES) is a symmetric key Block cipher that is used to provide data confidentiality in many embedded systems. Data confidentiality of each information is very important, either the information is related with bank account statements, credit card numbers, trade secrets, government documents or personal information. The confidentiality of a patient's physiological data is an important issue in traditional wireless body sensor networks (WBSNs) due to the limited hardware resources, which makes traditional WBSNs not suitable for the implementation of security mechanisms. The Xilinx FPGAs (Field Programmable Gate Arrays) is a suitable option for FPGA based WBSNs, because of the availability of more logic resources and better performance of FPGA. In this paper an FPGA based WBSN approach is discussed and an efficient implementation of AES is provided on latest Xilinx FPGAs (Artix-7, Virtex-7, Virtex-6, Virtex-4 and Spartan-6) that can be used to provide data confidentiality in FPGA based WBSNs. The presented efficient implementation technique of AES uses Block RAM resources of FPGA to get an optimized architecture with respect to power, speed and area. The results are provided in terms of throughput, slices, TPA and power. The XPA (Xilinx Power Analyzer) tool of Xilinx is used for power analysis.

Abstract: Security mechanisms to protect our systems and data from malicious adversaries have become essential. Strong encryption algorithms are an important building block of these solutions. However, each application has its own requirements and it is not always possible to find a cipher that meets them all. This work compares unrolled combinatorial hardware implementations of six lightweight block ciphers, along with an AES implementation as a baseline. Up until now, the majority of such ciphers were designed for area-constrained environments where speed is often not crucial, but recently the need for single-cycle, lowlatency block ciphers with limited area requirements has arisen to build security architectures for embedded systems. Our comparison shows that some designers are already on this track, but a lot of work still remains to be done.

Abstract: AES (Advanced Encryption Standard) is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting data. In this paper, we present three hardware architectures for AES, namely Serial/Serial, Parallel /Serial and Parallel/Pipelined. These architectures can be used as IP (Intellectual Property) cores in hybrid cryptosystem RSA-AES implemented on an FPGA PSoC (Programmable System on Chip). The highlights of our work are: implementing S-Box memories of AES SubBytes transformation on Slices of FPGA which reduces the hardware resources and using the Xtime() functions in the implementation of AES MixColumns transformation which accelerate its execution time. Such architectures cater to different applications and offer good tradeoffs between performances and occupied areas.

Abstract: In this paper, a high throughput modified Advanced Encryption Standard (AES)-128 bit algorithm is implemented. A new increased parallelism technique is introduced in modified AES architecture in Mix Column round which increases the overall throughput of AES algorithm. This technique is implemented in XC5VLX50T FPGA device Virtex-5. Using this technique throughput is increased 5 % and area is decreased by 30 % when compared to parallel mixcolumn.

Abstract: This paper presents implementation of S-Box for Advanced Encryption Standard (AES) algorithm. The proposed design structure is implemented in verilog. Previous works rely on lookup tables to implement the S-Box of AES algorithm which incurred a fixed and unbreakable delay. The proposed design employs combinational logic based composite field arithmetic AES S-Box which results in optimized area in terms of FPGA slices compared to ROM based lookup table. The proposed 4-stage pipelined implementation of S-Box is carried on the XC3S100E device of Xilinx FPGA with verilog code which requires 34 slices and 67 4-input LUTs and also maximum clock frequency of 187.071 MHz.

Abstract: Since the standardization of AES/Rijndael symmetric-key cipher by NIST in 2001, it gained widespread acceptance in various protocols and withstood intense scrutiny from the theoretical cryptanalysts. From the physical implementation point of view, however, AES remained vulnerable. Practical attacks on AES via fault injection, differential power analysis, scan-chain and cache-access timing have been demonstrated so far. Along this line, in this paper, we propose a novel and effective attack, termed Trace Buffer Attack. Trace buffers are extensively used for post-silicon debug of digital designs. We identify this as a source of information leakage and show that, unless proper countermeasure is taken, Trace Buffer Attack is capable of partially recovering the secret keys of different AES implementations. We report the detailed process of trace-buffer attack with experimental results. We also propose a countermeasure in order to avoid such attack.

Abstract: For ensuring the security of the information transmission, safe encryption algorithms are needed to encrypt information in wireless communication networks. Currently, one relative common encryption algorithm is AES encryption algorithm. However, AES encryption algorithm is public, which brings many problems to its security. To solving the safe problem of AES encryption algorithm, one improved AES encryption based on chaos theory is proposed. Simulation is also conducted by MATLAB to verify the feasibly and security of the proposed improved AES encryption.

Abstract: A new Transient-Steady Effect attack on block ciphers called TSE attack is presented in this paper. The concept of transient-steady effect denotes the phenomenon that the output of a combinational circuit keeps a temporal value for a while before it finally switches to the correct value. Unlike most existing fault attacks, our attack does not need a large amount of encryptions to build a statistical model. By injecting a clock glitch to capture the temporal value caused by transient-steady effect, attackers can obtain the information of key from faulty outputs directly. This work shows that AES implementations, which have transient-steady property, are vulnerable to our attack. Experiments are successfully conducted on two kinds of unmasked S-boxes and one kind of masked S-box implemented in serial with FPGA board. After a moderate pre-computation, we need only 1 encryption to recover a key byte of the unmasked S-boxes, and 20 encryptions to recover a key byte of the masked S-box. Furthermore, we investigate the key recover method for parallel unmasked implementation, and discuss a possible attack scenario which may deem WDDL-AES insecure.

Abstract: This paper presents an efficient ASIC implementation of the low area 8-bit AES encryption core using an optimized SBox for wireless networks. The proposed AES core supports 128- bit key length and 128-bit data blocks. The implementation results in a 90nm CMOS standard library show that the proposed AES encryption core has the maximum clock frequency of 452.5 MHz and higher resource usage efficiency compared with other designs.

Abstract: This paper describes the FPGA implementation of chaotic based advanced encryption standard (AES) using pipeline technique. The algorithm is a combination of chaotic maps and AES. In the proposed architecture, AES key is generated by chaotic maps and encryption is done by AES. The internal operations of each round of AES are optimized and parallel RAMs are used to implement the Sub-Bytes operation. Key expansion unit is synchronized with round unit which generate round key in each clock cycle. The key is stored and read from the key RAM in the same clock cycle which increases the speed. The proposed architecture is implemented using Verilog HDL and Xilinx ISE Design Suite 14.5. Implementation results are compared with previously reported pipelined AES architectures on same FPGA devices. The comparison results show that our proposed architecture is efficient in terms of speed and area.

Abstract: In this paper, the S-Box of Advance Encryption Standard(AES) are computed using cellular automata whereas standard AES algorithm S-Box are computed using irreducible polynomial equation in table form known as look up ta-bles(LUTs). Using Cellular Automata (CA) based S-Box makes the algorithm more secure, more robust and dynamic. The security aspects of the S-Box used in AES algorithm are evaluated using cryptographic properties like Strict Avalanche Criteria, Non Linearity, Entropy and Common Immunity Bias. The design of S-Box using Cellular Automata is better with respect to security and dynamic aspect compared w.r.t to the classical S-boxes used in standard Data Encryption Standard and Advance Encryption Standard.

Abstract: Now a days, the number of Internet and wireless communications users has rapidly grown and that increases demand for security measures to protect user data transmitted over openchannels. Cryptographic algorithms are very essential for security of the systems worldwide. In December 2001, the National Institute of Standards and Technology (NIST) of the United States selected the Rijndael algorithm as the suitable Advanced Encryption Standard (AES) to replace the Data Encryption Standard (DES) algorithm. AES can be considered the most widely used modern symmetric key encryption standard. The AES algorithm is a block cipher that can encrypt and decrypt digital information. This paper explores task level parallelism with three concurrently working AES modules to achieve less area and high throughput. With the area optimization techniques, the system becomes area and time efficient as the throughput of 5.751Gbps is achieved with less area. The design is implemented in Zynq(xc7z020-2clg484) device and tested on Zedboard. As three different implementations of AES are explored, the design has three times higher throughput with less area than the other systems. To encrypt/decrypt a file using the AES algorithm, the file must undergo a set of complex computational steps. Therefore a software implementation of AES algorithm would be slow and consume large amount of time to complete. The immense increase of both stored and transferred data in the recent years had made this problem even more serious when the need to encrypt/decrypt such data arises.

Abstract: The implementation of the SubBytes (or S-Box) step of the AES algorithm significantly contributes to the area, delay, and power of AES accelerators. Unlike typical logic gate S-Box implementations, we use full-custom 256×8-bit ROMs, which significantly improve performance and efficiency. We implemented a fully-unrolled, pipelined AES-128 encryption accelerator using ROM-based S-Boxes in 65nm bulk CMOS which operates at 2.2GHz and consumes 523mW at 1.0V, 27°C. In counter-mode operation (CTR), the throughput is 275.2Gbps, which is 5.2x higher than the highest ever reported in the literature to our knowledge.

Abstract: In this paper we study the information leakage that may exist, due to electrical coupling, between logically independent blocks of a secure circuit as a new attack path to retrieve secret information. First, an aes-128 has been implemented on a fpga board. Then, this aes implementation has been secured with a delay-based countermeasure against fault injection related to timing constraints violations. The countermeasure's detection threshold was supposed to be logically independent from the data handled by the cryptographic algorithm. Thus, it theoretically does not leak any information related to sensitive values. However experiments point out an existing correlation between the fault detection threshold of the countermeasure and the aes's calculations. As a result, we were able to retrieve the secret key of the aes using this correlation. Finally, different strategies were tested in order to minimize the number of triggered alarm to retrieve the secret key.

Abstract: An Image Encryption and Decryption Using AES (Advance Encryption Standard) Algorithm is proposed in this paper. Due to increasing use of image in various field, it is very important to protect the confidential image data from unauthorized access. The design uses the iterative approach with block size of 128 bit and key size of 256 bit. The numbers of round for key size of 256 bits is 14. As secret key increases the security as well as complexity of the cryptography algorithms.This paper presents a algorithm in which the image is an input to AES Encryption to get the encrypted image and the encrypted image is the input to AES Decryption to get the original image.

Abstract: In this paper, we present a new pipelined 8-bit architecture for Advanced Encryption Standard (AES) encryption. The new architecture supports encryption with 128-bit keys with 10 rounds of Byte Substitution, Shift Rows, Mix Columns and Add Round Key operations. We emphasized on optimizing a single round by using an 8-bit architecture instead of 128-bit architecture which resulted into overall optimization and increase in bit security of the system. We have also proposed a new architecture for Key Expansion Unit and S-Box (Substitution Box) using a more secure key expansion algorithm and high order masking respectively, hence making the overall architecture of AES more secure and less prone to Differential Power Analysis (DPA) attacks. The proposed architecture was implemented on Virtex-7 working at a maximum clock frequency of 191.42 MHz with a throughput of 94.24 Mbps and a power consumption of 0.694 W.

Abstract: The securityof videoapplications such as commercial videos, military videos and othershave become an important field of research recently. One of the most secure algorithms is Advanced Encryption Standard (AES) algorithm;however this algorithm is inefficient for dealing with video encryption due to its slowness property. This paper proposes a new modifiedof AES to make it more suitable for encrypting digital video. The Modification focuses on the slowest transformations in original AES which is mix columnstransformationsand replace them with newHenon map chaoticbased mask and one mix columns transformation. Resulting in a significant reduction in encryption and decryption time and enhance the security level of AES algorithm, and also the key space is increased as observed in the simulation results of proposed system. Keywords: AES-128, Chaotic mask, Henon map, Sub-Byte, Mix columns.

Abstract: A new authenticated encryption algorithm Minalpher [1] submitted to CAESAR (Competition for Authenticated Encryption: Security, Applicability, and Robustness) [2] was implemented on various FPGA devices with straightforward and pipelined hardware architectures. Then, its performances in operating speed, hardware size, and power consumption were compared with a current standard algorithm AES-GCM [3] to show the advantages of Minalpher in compact and high-speed hardware implementations.

Abstract: With worldwide communication of the private and confidential data over the computing networks or internet, there is always a chance of threat of data confidentality, data integrity and also of data availability. Information has become one of the most important assests in growing demand of need to store every single importance of events in everyday of our life. Encipherment is one of the important security mechanism to protect the data from public access. Encryption will convert the data in such a manner that only a person who has special knowledge of reading it can be able to read it. The Advanced Encryption Standard (AES) is considered to be the strongest encryption technique in cryptography. Advanced Encryption Standard (AES) is a symmetric key block cipher which will encrypt as well as decrypt the data block. Advanced Encryption Standard (AES) can be implemented in both software and hardware. As compared to software implementation hardware implementation of AES has an advantage of increased throughput and more security. In this paper we have presented the FPGA based implementation of 128-bit Advanced Encryption Standard (AES) using fully pipelined architecture. Our proposed architecture can deliver higher throughput at both encryption and decryption operations. Xilinx ISE design suite 13.1 is used for design and Spartan-3 for implementation.

Abstract: Data protection in mobile as well as in computer networks is increasing day by day forcing developer to design the cryptographic algorithms. Also sending data securely over a transmission link is important in many applications. To solve this security issue the U.S. government adopted an algorithm Advanced Encryption Standard (AES) and is now used worldwide. As there is possibility that this algorithm may get hacked, hence this Paper presents the hardware for AES algorithm which can be implemented on Xilinx FPGA. The approach used to implement the AES algorithm is the use of Look Up Tables (LUTs). This approach will give the throughput be-tween 3Gbps to 4Gbps with minimum utilization of resources on FPGA. Results can be verified using appropriate CAD tools.