Abstract: The technical analysis used in determining which of the Advanced Encryption Standard candidates will be selected as the Advanced Encryption Algorithm includes eciency testing of both hardware and software implementations of candidate algorithms. Reprogrammable devices such as Field Programmable Gate Arrays (FPGAs) are highly attractive options for hardware implementations of encryption algorithms as they provide cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions. This contribution investigates the signicance of FPGA implementations of four of the Advanced Encryption Standard candidate algorithm nalists. Multiple architectural implementation options are explored for each algorithm. A strong focus is placed on high throughput implementations, which are required to support security for current and future high bandwidth applications. The implementations of each algorithm will be compared in an eort to determine the most suitable candidate for hardware implementation within commercially available FPGAs.

Abstract: In this paper we study and compare the performance of FPGA-based implementations of the five final AES candidates (MARS, RC6, Rijndael, Serpent, and Twofish). Our goal is to evaluate the suitability of the aforementioned algorithms for FPGA-based implementations. Among the various time-space implementation tradeoffs, we focused primarily on time performance. The time performance metrics are throughput and key-setup latency. Throughput corresponds to the amount of data processed per time unit while the key-setup latency time is the minimum time required to commence encryption after providing the input key. Time performance and area requirement results are provided for all the final AES candidates. To the best of our knowledge, we are not aware of any published results that include key-setup latency results. Our results suggest that Rijndael and Serpent favor FPGA implementations the most since their algorithmic characteristics match extremely well with the hardware characteristics of FPGAs.

Abstract: With the expiration of the Data Encryption Standard (DES) in 1998, the Advanced Eneryption Standard (AES) development process is well underway. It is hoped that the result of the AES process will be the specification of a new non-classified encryption algorithm that will have the global acceptance achieved by DES as well as the capability of long-term protection of sensitive information. The technical analysis used in determining which of the potential AES candidates will be selected as the Advanced Encryption Algorithm includes efficiency testing of both hardware and software implementations of candidate algorithms. Reprogrammable devices such as Field Programmable Gate Arrays (FPGAs) are highly attractive options for hardware implementations of encryption algorithms as they provide cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions. This contribution investigates the significance of an FPGA implementation of Serpent, one of the Advanced Encryption Standard candidate algorithms. Multiple architecture options of the Serpent algorithm will be explored with a strong focus being placed on a high speed implementation within an FPGA in order to support security for current and future high bandwidth applications. One of the main findings is that Serpent can be implemented with encryption rates beyond 4 Gbit/s on current FPGAs.

Abstract: This paper presents an evaluation of five Round 2 Advanced Encryption Standard (AES) candidates from the viewpoint of their realization in a FPGA. After the analysis of the general characteristics of the algorithms a general cipher structure is defined. Using this structure, the suitability of available FPGA families is evaluated. Finally, three algorithms – RIJNDAEL [5], SERPENT [6] and TWOFISH [7] are realized in VHDL and implemented in the selected FPGA family.

Abstract: Each of the finalist algorithms appears to offer adequate security, and each offers a considerable number of advantages. Any of the finalists could serve admirably as the AES. However, each algorithm also has one or more areas where it does not fare quite as well as some other algorithm; none of the finalists is outstandingly superior to the rest. – Nechvatal, Barker, Bassham, Burr, Dworkin, Foti, Roback [12]

Abstract: FPGAs have proven to be very effective and efficient devices on which to implement encryption algorithms. They perform at much faster data-rates and provide better security than equivalent software implementations. They also provide more flexibility than ASIC implementations. This paper presents a high performance silicon intellectual property (IP) core for the data encryption standard (DES) encryption algorithm. The 16-stage pipelined DES design runs at an encryption rate of 3.87 Gbits/s using Xilinx Virtex FPGA technology making this the fastest single-chip DES FPGA implementation reported to date. This result is a factor 28 times faster than software implementations.

Abstract: Each of the current five candidate algorithms for AES satisfies a different balance of these constraints; the ‘best’ algorithm depends on circumstances, which are impossible to know beforehand. Furthermore, one of the principal requirements that of security of the algorithm cannot easily be measured; subjective judgements therefore must be made (based, for instance, on notions of ‘safety margin’ or ‘conservative design’) which may prove to be inaccurate or irrelevant in years to come.