Adder–subtractor

Abstract: Reversible arithmetic units such as adders, subtractors and comparators form the essential components of any hardware implementation of quantum algorithms such as Shor's factoring algorithm. Further, the synthesis methods proposed in the existing literature for reversible circuits target combinational and sequential circuits in general and are not suitable for synthesis of reversible arithmetic units. In this paper, we present several design methodologies for reversible subtractor and reversible adder-subtractor circuits, and a framework for synthesizing reversible arithmetic circuits. Three different design methodologies are proposed for the design of reversible ripple borrow subtractor that vary in terms of optimization of metrics such as ancilla inputs, garbage outputs, quantum cost and delay. The first approach follows the traditional ripple carry approach while the other two use the properties that the subtraction operation can be defined as $$a-b$$ = $$\overline{\bar{a}+b}$$ and $$a-b$$ = $${a+\bar{b}+1}$$, respectively. Next, we derive methodologies adapting the subtractor to also perform addition as selected with a control signal. Finally, a new synthesis framework for automatic generation of reversible arithmetic circuits optimizing the metrics of ancilla inputs, garbage outputs, quantum cost and the delay is presented that integrates the various methodologies described in our work.

Abstract: The quest continues for microelectronic implementations with higher throughput and reduced power consumption, particularly for digital signal processing, graphic processing unit and CPU portable applications. This Letter focuses on the digital multiplier circuit, which is a key component in determining the power-delay-product for numerous battery powered applications. A proposed radix-4 8 × 8 Booth multiplier is implemented using four stages with a unique optimised stage-1 architecture. Instead of using adder/subtractor in stage-1, it is replaced with a novel binary-to-2's complement converter and a 2:1 MUX to reduce the delay and power consumption by 7.08 and 49.46%, respectively, compared to the other stages. The proposed design is implemented using CMOS 90 nm technology with 1.2 V supply to demonstrate performance.

Abstract: An apparatus that performs arithmetic logic and carry-lookahead logic in parallel on two N-nary operands, including saturating or unsaturating, signed or unsigned, addition or subtraction. The operands may be selectably partitioned into 8-bit, 16-bit, 32-bit, or 64-bit operands. For multiple partitions, carry propagation is interrupted on partition boundaries. Each selectable feature may be implemented singly, or in combination with other selectable features.

Abstract: In recent years, Quantum Electronics and Reversible Logic have emerged as a major area of research having applications in low power CMOS circuits, cryptography, optical computing and nanotechnology. The fact that classical logic gates such as AND, OR, XOR etc., barring the NOT gate, cannot predict the input given the output and hence generate heat due to information loss, has given rise to the concept of reversible logic. In this paper, a new reversible 4 * 4 “SCG” gate has been proposed which is being used to realize the classical set of logic gates in the reversible domain. The most promising fact of the proposed gate is that a single SCG gate can be used to realize a reversible Full Adder/Subtractor circuit or a single bit reversible Comparator. It has been shown that the Full Adder/Subtractor and the single bit Comparator using the proposed gate is much better and optimized in terms of number of garbage outputs and the number of reversible gates used in comparison to the existing counterparts in literature. Further efficient Reversible Parallel Adder/Subtractor circuits and Match Logic have been designed using the proposed SCG gate. Also a 4-bit digital comparator has been designed by cascading a series of single bit comparators using SCG gate. General Terms Architecture, Logic Design, Reversible Logic Gate.