Showing papers on "Active load published in 2009"
TL;DR: The CPC-FEM is capable of predicting the generated output power of the EHD with different load resistor values while simultaneously calculating the effect of the load resistor value on the displacement amplitude of the tip of the cantilever, making the model invaluable for validating the performance of a designed EHD before it is fabricated and tested, thereby reducing the recurring costs associated with repeat fabrication and trials.
Abstract: This paper presents, for the first time, a coupled piezoelectric-circuit finite element model (CPC-FEM) to analyze the power output of a vibration-based piezoelectric energy-harvesting device (EHD) when it is connected to a load resistor. Special focus is given to the effect of the load resistor value on the vibrational amplitude of the piezoelectric EHD, and thus on the current, voltage, and power generated by the device, which are normally assumed to be independent of the load resistor value to reduce the complexity of modeling and simulation. The presented CPC-FEM uses a cantilever with a sandwich structure and a seismic mass attached to the tip to study the following characteristics of the EHD as a result of changing the load resistor value: 1) the electric outputs: the current through and voltage across the load resistor; 2) the power dissipated by the load resistor; 3) the displacement amplitude of the tip of the cantilever; and 4) the shift in the resonant frequency of the device. It is found that these characteristics of the EHD have a significant dependence on the load resistor value, rather than being independent of it as is assumed in most literature. The CPC-FEM is capable of predicting the generated output power of the EHD with different load resistor values while simultaneously calculating the effect of the load resistor value on the displacement amplitude of the tip of the cantilever. This makes the CPC-FEM invaluable for validating the performance of a designed EHD before it is fabricated and tested, thereby reducing the recurring costs associated with repeat fabrication and trials. In addition, the proposed CPC-FEM can also be used for producing an optimized design for maximum power output.
137 citations
6 Nov 2009
TL;DR: In this paper, two interleaved LLC series resonant converter (LLC-SRC) structures are proposed to reduce the output current ripple in a multi-phase interleaving LLC SRC.
Abstract: Recently, the LLC series resonant converter (LLC-SRC) is widely used for many applications because it has many advantages over other power converters. To apply LLC- SRC to high current application, it is necessary to interleaved operation to reduce output current ripple. Moreover, output current should be shared equally. However, active load share technique cannot be applied to output current divide equally because LLC SRC is regulated with frequency. Therefore, design of multi-phase interleaved LLC SRC is required that load current haring can be realized automatically. In this paper, two structures for interleaved LLC SRC are suggested. In the point of load share, two structures are analyzed. In order to verify proposed analyze, the laboratory experiments are executed and discussed with a 480W prototype.
81 citations
9 Oct 2009
TL;DR: The analysis, design, and measurement results of a high-gain, low-noise differential transimpedance amplifier designed to interface with electrostatic Microelectromechanical Systems (MEMS) resonators are presented.
Abstract: We present the analysis, design, and measurement results of a high-gain, low-noise differential transimpedance amplifier (TIA) designed to interface with electrostatic Microelectromechanical Systems (MEMS) resonators A capacitive-feedback current amplifier drives current into an active load to obtain a 56 Mμ transimpedance gain, 18 MHz bandwidth, phase response near 0°, and 65 fA/√Hz input-referred noise The TIA was fabricated in 018 µm CMOS technology and dissipates 436μW from a 18V supply
62 citations
Patent•
13 May 2009TL;DR: In this article, a method and a remote device such as a sealed expansion module (SEM) for reducing power dissipation from an input power source in a telecommunications system are disclosed.
Abstract: A method and a remote device such as a sealed expansion module (SEM) for reducing power dissipation from an input power source in a telecommunications system are disclosed. A SEM contains a network feed monitor that receives an input voltage and current on twisted wire pair cables. The input voltage is then transmitted to a DC/DC converter and the voltage is adjusted and then transmitted to a BUS feed monitor connected to an active load. A first I2C device is connected to the network feed monitor to provide information related to input voltage and current to a main microprocessor that calculates input power. A second I2C device is connected to the BUS feed monitor and the active load to provide information related to the output voltage and output current to the main microprocessor that calculates output power. The main microprocessor is further connected through a third I2C device to a digital power manager that provides a DAC trim output to the DC/DC converter for optimizing the efficiency of the system.
47 citations
Patent•
6 Mar 2009TL;DR: In this paper, the authors provided a semiconductor integrated device including a level-shifting circuit including: a first and a second input nodes; and a first-and-second output nodes.
Abstract: According to an aspect of the present invention, there is provided a semiconductor integrated device including: a level-shifting circuit including: a first and a second input nodes; and a first and a second output nodes; a first current mirror circuit connected with the first output node; a second current mirror circuit connected with the second output node; a first switch circuit series-connected with an input-side of first current mirror circuit; a second switch circuit series-connected with an input-side of the second current mirror circuit; a fifth switching element parallel-connected with the input-side of the first current mirror circuit; and a sixths switching element parallel-connected with the input-side of the second current mirror circuit.
40 citations
Patent•
24 Sep 2009TL;DR: Load detection circuitry is provided that may be used to monitor an output line as mentioned in this paper, where a switch may be interposed between the current sensing resistor and the output line to determine whether an electronic device or other load is attached.
Abstract: Load detection circuitry is provided that may be used to monitor an output line. The load detection circuitry may include one or more current sensing resistors. A monitor circuit can measure voltages across the current sensing resistors to determine whether current is flowing through a load connected to the output line. In configurations with multiple different current sensing resistors, the monitor circuit can determine the amount of current that is flowing through the load based on the measured voltages. A switch may be interposed between the current sensing resistor and the output line. A current-limited voltage regulator may supply a voltage to the output line. The monitor circuit may periodically open the switch and monitor resulting voltage changes on the output line to determine whether an electronic device or other load is attached. Opening of the switch may be inhibited whenever current is sensed through a current sensing resistor.
35 citations
TL;DR: In this article, the authors proposed an active power compensation scheme to compensate for the active power change as well as providing reactive power support in a weak network, which can reduce phase jumps and magnitude deviations of the bus voltage under load disturbances.
Abstract: The voltage at the point of common coupling (PCC) in a weak network is very sensitive to load changes. A sudden change in active load will cause both a phase jump and a magnitude fluctuation in the bus voltage (voltage at the PCC), whereas reactive load changes mainly affect the voltage magnitude. With the addition of energy storage to a static synchronous compensator (STATCOM), it is possible to compensate for the active power change as well as providing reactive power support. In this paper effective active power compensation schemes are proposed. Simulation and experimental results verify the compensation schemes by showing that a STATCOM with energy storage can significantly reduce phase jumps and magnitude deviations of the bus voltage under load disturbances.
31 citations
7 Jun 2009
TL;DR: In this paper, the results of dynamic load modulation on a high power amplifier are shown with experiments with a simple static nonlinear model as an inverse model, and by dynamically controlling both the input signal to the power amplifier and the load impedance, high efficiency operation of the power amplifiers is achieved.
Abstract: In this paper, the results of dynamic load modulation on a high power amplifier is shown with experiments. A simple static nonlinear model is used as an inverse model, and by dynamically controlling both the input signal to the power amplifier and the load impedance, high efficiency operation of the power amplifier is achieved. The modulated measurements show the feasibility of dynamic load modulation for practical high power, high frequency applications.
25 citations
Patent•
1 Apr 2009TL;DR: In this paper, a wideband analog-to-digital conversion block is provided for obtaining measurement data, where first and second injection signal generators (7, 8) are connected to a source side and a load side of the device under test, respectively.
Abstract: Measurement arrangement and method for active load pull measurements of a device under test (1). A wideband analog-to-digital conversion block (3) is provided for obtaining measurement data. First and second injection signal generators (7, 8) are connected to a source side and a load side of the device under test (1). This set up allows to create predetermined reflection coefficients at reference planes of the device under test (1). Injection signal parameters as determined are converted into the injection signals at the source and load side by digital-to-analog conversion. The wideband analog-to-digital conversion block (3) is further arranged for analog-to-digital conversion of the intermediate frequency signals to obtain the actual measured reflection coefficient versus frequency functions with a first frequency resolution. The first frequency resolution applied in the analog-to-digital conversion is equal to or better than a second frequency resolution applied in the digital-to-analog conversion.
19 citations
TL;DR: In this article, a load-pull measurement data obtained from AlGaN/GaN HEMTs under the class-B operation reveal that there exist optimal loads for pulsed-IV/RF condition, which differ from the ones found for a dc-IV and continuous wave condition.
Abstract: A novel pulsed class-B load-pull measurement system is developed to characterize GaN HEMTs targeting the design of high-efficiency class-B or class-C power amplifiers operating under a pulsed-bias and pulsed-RF (pulsed-IV/RF) condition. Based on a large-signal network analyzer, the test system uses an active load-pull method to provide stable open-loop pulsed-RF loads into the drain at omega0 and 2omega0 while bypassing slow-memory effects. The load-pull measurement data obtained from AlGaN/GaN HEMTs under the class-B operation reveal that there exist optimal loads for pulsed-IV/RF condition, which differ from the ones found for a dc-IV and continuous wave condition. This is due to the avoidance of slow-memory effects in the pulsed-IV/RF load-pull measurements, which are known to degrade the device RF performance: a 2-dB increase in output power is obtained for a GaN HEMT on sapphire. The optimized pulsed-RF active load for a GaN HEMT on SiC demonstrates a power-added efficiency of 82% with 17.8-dBm output power under quasi class-B pulsed operation at 2 GHz.
14 citations
TL;DR: To enhance circuit bandwidth for 10-GB/s operation, several techniques include active load inductive peaking and active feedback with current buffer in Cherry-Hooper topology and it reduces 30%-65% of the chip area comparing with on-chip inductor peaking method.
Abstract: A 10-Gb/s current mode logic (CML) input/output (I/O) circuit for backplane interconnect is fabricated in 0.18-mu m 1P6M CMOS process. Comparing with conventional I/O circuit, this work consists of input equalizer, limiting amplifier with active-load inductive peaking, duty cycle correction and CML output buffer. To enhance circuit bandwidth for 10-GB/s operation, several techniques include active load inductive peaking and active feedback with current buffer in Cherry-Hooper topology. With these techniques, it reduces 30%-65% of the chip area comparing with on-chip inductor peaking method. This design also passes the interoperability test with switch fabric successfully. It provides 600- mVpp differential voltage swing in driving 50-Omega output loads, 40-dB input dynamic range, 40-dB voltage gain, and 8-mV input sensitivity. The total power consumption is only 85 mW in 1.8-V supply and the chip feature die size is 700 mum times 400 mum.
Patent•
17 Dec 2009TL;DR: In this article, an apparatus is provided for an electronic device that includes a dynamic electrical load, a secondary power coil receiver module that inductively receives a current from a primary coil of an power conversion system, a means for monitoring a current in the secondary receiver module being delivered to the dynamic load and a current limiter circuit that limits the current to the static load based upon the measured charging current.
Abstract: An apparatus is provided for an electronic device. The apparatus includes a dynamic electrical load, a secondary power coil receiver module that inductively receives a current from a primary coil of an power conversion system, a means for monitoring a current in the secondary receiver module being delivered to the dynamic load, a means for transmitting a power control signal to the power conversion system through the secondary charging coil, a current monitoring circuit that measures a current delivered to the dynamic load and a current limiter circuit that limits the current to the dynamic load based upon the measured charging current.
Patent•
1 Dec 2009TL;DR: In this article, a circuit arrangement with a load current path and a load transistor having a first and a second load path terminal and a control terminal is presented, where the control terminals and first load path terminals of the load transistor and the measuring transistor are coupled.
Abstract: One aspect is a circuit arrangement having a load current path with a load transistor having a first and a second load path terminal and a control terminal. A first measurement current path includes a measuring transistor having a first and a second load path terminal and a control terminal. The control terminals and first load path terminals of the load transistor and the measuring transistor are coupled. A first regulating circuit has a controllable resistor and is designed to drive the resistor depending on electrical potentials at the second load path terminals of the load transistor and of the measuring transistor. A current mirror circuit is coupled between the first measurement current path and a second measurement current path. A deactivation circuit is designed to deactivate the first regulating circuit depending on a current flowing through the measuring transistor.
Patent•
27 Aug 2009
TL;DR: In this paper, a solar cell characteristic measuring device is used to measure the output characteristics of the solar cell while avoiding junction capacitance, and an operation point control element divides the magnitude of the load, taken from the solar cells, of the electronic load device into a plurality ranging from states of opening to short-circuiting, while driving the load device in the load circuit periodically and intermittently, changing the load magnitude stepwise and controlling the operation point of the sun cell.
Abstract: A solar cell characteristic measuring device measures the output characteristics of a solar cell while avoiding junction capacitance. The device provides a solar cell load circuit by connecting the solar cell with an electronic load device setting a load current or voltage variably, and a measurement circuit connecting voltage and current detectors with the load. An operation point control element divides the magnitude of the load, taken from the solar cell, of the electronic load device into a plurality ranging from states of opening to short-circuiting, while driving the load device in the load circuit periodically and intermittently, changing the load magnitude stepwise and controlling the operation point of the solar cell, and a processing element reading and processing the detected values of the voltage and current detectors at each drive period of the electronic load device and for the period of the stable output voltage of the solar cell.
Patent•
12 Jan 2009
TL;DR: In this article, a resistor unit is adapted for use in a constant current source circuit or a temperature compensating circuit for providing temperature compensation to a constant voltage reference circuit, where the resistor unit includes at least one first resistor and at least two second resistors coupled to the first resistor.
Abstract: A resistor unit is adapted for use in a constant current source circuit or a temperature compensating circuit for providing temperature compensation to a constant voltage reference circuit. The resistor unit includes at least one first resistor, and at least one second resistor coupled to the first resistor. One of the first and second resistors is a positive temperature coefficient resistor. The other one of the first and second resistors is a negative temperature coefficient resistor. Because a temperature characteristic of the first resistor is opposite to that of the second resistor, an effective resistance of the resistor unit changes in a relatively narrower range with temperature.
Patent•
6 Apr 2009
TL;DR: In this paper, the authors present a method, system and current limiting circuit configured to limit the excess output current passing through a load, which is a resistor connected in series with said load and in parallel with a switch, wherein said switch is turned ON, thereby shorting said resistor, when the output voltage applied to said load is decreased by a predetermined level.
Abstract: The present invention relates to a method, system and current limiting circuit configured to limit the excess output current passing through a load, said current limiting circuit comprising a resistor connected in series with said load and in parallel with a switch, which is initially turned OFF, wherein said switch is turned ON, thereby shorting said resistor, when the output voltage applied to said load is decreased by a predetermined level.
Patent•
25 Sep 2009
TL;DR: In this article, a driving circuit of a load has an output semiconductor element connected in series in a power supply path from a power source to the load, to control a current of the load.
Abstract: A driving circuit of a load has an output semiconductor element connected in series in a power supply path from a power source to the load, to control a current of the load, a PWM signal generator for controlling ON/OFF of the output semiconductor element, a driver of the output semiconductor element according to the PWM signal, a detection resistor made of a semiconductor detecting a current of the load, a current output amplifier outputting a monitored current of detection resistor without being influenced by variation of ambient temperature, a resistor converting the monitored current into a monitored voltage, a current source outputting a constant current without being influenced by variation of ambient temperature, a resistor outputting a reference voltage according to the constant current, and an A/D converter converting the monitored voltage according to the reference voltage into a detected current value of the current of the load.
Patent•
18 Mar 2009
TL;DR: In this paper, a sense amplifier is coupled to the positive side of the first resistor via a first pin of the sense amplifier, and coupling to the negative side of a first resistor through the second resistor through a second resistor via the second pins of the senses amplifier.
Abstract: A current sensing circuit includes a first resistor, a second resistor and a sense amplifier. The first resistor converts a current flowing through the first resistor to a voltage drop between positive and negative sides of the first resistor. The second resistor is coupled to the negative side of the first resistor. The sense amplifier is coupled to the positive side of the first resistor via a first pin of the sense amplifier, and coupled to the negative side of the first resistor through the second resistor via a second pin of the sense amplifier. The sense amplifier employs a negative feedback to generate a sensing current proportional to the current flowing through the first resistor.
Patent•
14 Jul 2009TL;DR: In this paper, a control circuit was proposed to control a driving transistor connected in series with an electrical load between a power supply voltage and a ground, including a pull-up resistor connected at one end to a voltage side of the driving transistor, a current detection resistor for detecting an electric current flowing from the driver to the ground, and a current mirror circuit including a starting transistor connected between the pullup transistor and the current detector resistor.
Abstract: A control circuit controls a driving transistor connected in series with an electrical load between a power supply voltage and a ground. The control circuit includes a pull-up resistor connected at one end to a power supply voltage side of the driving transistor, a current detection resistor for detecting an electric current flowing from the driving transistor to the ground, a current mirror circuit including a starting transistor connected between the pull-up transistor and the current detection resistor. The current mirror circuit supplies a mirror current of the electric current. The control circuit further includes a current source circuit for supplying a driving current to a control terminal of the driving transistor in accordance with the mirror current to turn ON the driving transistor in response to an external control signal.
Patent•
NEC1
TL;DR: In this paper, an impedance adjustment circuit including a comparator and a resistor control circuit is described, where the comparator compares the resistance value of an external resistor and that of a replica resistor that forms a replica of a terminal resistor.
Abstract: Disclosed is an impedance adjustment circuit including a comparator and a resistor control circuit. The comparator compares the resistance value of an external resistor and that of a replica resistor that forms a replica of a terminal resistor. The resistor control circuit includes a replica resistor control counter, a resistor-under-adjustment control signal holding circuit and a monitor circuit. The replica resistor control counter counts up and down based on the comparison result by the comparator to output a control signal to the replica resistor. The resistor-under-adjustment control signal holding circuit holds a control signal that is delivered to the terminal resistor. The monitor circuit receives the state of the counter and an output of the retention circuit and, in case the difference between the count state of the replica resistor control counter and an output of the resistor-under-adjustment control signal holding circuit is within a preset range, delivers the output of the resistor-under-adjustment control signal holding circuit as an input to the resistor-under-adjustment control signal holding circuit.
24 May 2009
TL;DR: A design technique of low power fully CMOS low-dropout voltage regulator (LDO) based on quick response (QR) circuit based on CMOS technology can achieve a fast load transient responses with less transient overshoot or undershoot when driving a large load current.
Abstract: In this work, we propose a design technique of low power fully CMOS low-dropout voltage regulator (LDO) based on quick response (QR) circuit to improve the load transient response. Implemented in 0.18µm CMOS technology, the LDO with proposed QR circuit can achieve a fast load transient responses with less transient overshoot or undershoot when driving a large load current. For 1µF decoupling capacitor and 0.1mA-150mA load current change, the output undershoot and overshoot are 196mV and 172mV while the settling time is approximately 60µs and 65µs respectively . The proposed circuit dissipates a very low static power, with only 8.5µA for light load and 35µA for heavy load for output voltage VOUT = 1.2V and input voltage VDD = VOUT+1.0V . This includes the reference circuit, the over current protection circuit as well as the feedback network.
Patent•
5 May 2009TL;DR: In this paper, a switch sets a first time period and a second time period in connection states between the first and second transistors and the capacitances, so that a gate voltage of the first transistor is supplied to the first capacitance during the first period, and the second transistor voltage becomes an output time period of the operational amplifier during the second period.
Abstract: In an offset cancellation circuit according to the present invention, a first capacitance is connected to a gate of a first transistor of a first active load, and a second capacitance is connected to a gate of a second transistor of the first active load. A switch sets a first time period and a second time period in connection states between the first and second transistors and the first and second capacitances. The connection states between the first and second transistors and the first and second capacitances are set so that a gate voltage of the first transistor is supplied to the first capacitance, and a gate voltage of the second transistor is supplied to the second capacitance during the first time period; and so that the first and second capacitances can retain charges, and the second time period becomes an output time period of the operational amplifier during the second time period.
Patent•
16 Aug 2009
TL;DR: In this paper, a reference voltage generator consisting of a current generation circuit for producing a current, an active load circuit for receiving the current and outputting the reference voltage, and a reference level supply circuit for providing at least two reference voltage control levels by which the first and second reference voltage levels can adjust and maintain the reference level at a steady state.
Abstract: This invention relates to a reference voltage generator comprising: a current generation circuit for producing a current; an active load circuit for receiving the current and outputting a reference voltage, the active load circuit comprising at least a first reference voltage control circuit and a second reference voltage control circuit coupled thereto for lowering or boosting the level of the reference voltage; and a reference voltage level supply circuit for providing at least two reference voltage control levels by which the first and second reference voltage control circuits can adjust and maintain the reference voltage level at a steady state.
Patent•
23 Mar 2009
TL;DR: In this article, a DC-DC converter includes a chip including an error amplifier and a pulse width modulator (PWM) having an input connected to an output of the error amplifier, and an inductor driven by said PWM in series with an output node (V OUT ) of the converter, wherein a load current flows through the inductor.
Abstract: A DC-DC converter includes a chip including an error amplifier and a pulse width modulator (PWM) having an input connected to an output of the error amplifier, and an inductor driven by said PWM in series with an output node (V OUT ) of the converter, wherein a load current flows through the inductor. V OUT is fed back through a network including a feedback resistor (RFB) to an inverting input of the error amplifier. A circuit for sensing the load current includes a first operational amplifier, a sense resistor on the chip having resistance R SENSE coupled to an inverting input of the first amplifier; wherein a sense current related to the load current flows through the sense resistor, a dependent current source provides an output current to supply the sense current. A reference resistor is disposed on the chip having a resistance R REFERENCE which is a fixed multiple of R SENSE . A set resistor is provided having a resistance R SET . Tracking circuitry sets a voltage across the reference resistor to be equal to a voltage across the set resistor. A function block is coupled to receive a current through the set resistor and a current through the reference resistor to find their ratio. A current multiplier is provided, wherein an output of the function block is coupled to the current multiplier. The current multiplier provides a measurement current which is proportional to the load current divided by R SET .
Patent•
11 Aug 2009
TL;DR: The four-terminal resistor is characterized by having the capacity to adjust both resistance and temperature coefficient of resistance (TCR) during manufacturing process as discussed by the authors, and it can be divided into three or four elementary resistors R1-R3 forming a closed loop.
Abstract: Thermally stable four-terminal resistor is characterized by having the capacity to adjust both resistance and temperature coefficient of resistance (TCR), during manufacturing process. The four-terminal resistor includes 3 or 4 elementary resistors R1-R3 forming a closed loop. Resistor R1 is the principal low-ohmic value resistor. The terminals of resistor Rl serve as "Force" terminals of the four-terminal resistor. Resistors R2, R3 form a voltage divider intended to minimize the TCR of the four- terminal resistor and connected in parallel to resistor R1. The terminals of resistor R3 serve as "Sense" terminals of the four-terminal resistor. Resistor R2 may be split into two resistors: R2a, R2b connected in series to resistor R3 to simplify the implementation of four-terminal resistor. Elementary resistors R1, R2 must have the same sign of TCR. Target resistance and TCR minimization in four-terminal resistor are reached by adjustment of resistances of the elementary resistors.
Patent•
10 Feb 2009
TL;DR: A series load circuit is a circuit where a first load circuit and a light-emitting element unit 852 (a second load circuit) are connected in series as discussed by the authors, and a constant current circuit 110 supplies the series load circuits with a drive current for the light-EMitting unit 851.
Abstract: PROBLEM TO BE SOLVED: To reduce manufacturing cost, enhance the efficiency of power and improve reliability, in a power circuit which supplies power to a plurality of load circuits different in drive currents. SOLUTION: A series load circuit is a circuit where a light-emitting element unit 851 (a first load circuit) and a light-emitting element unit 852 (a second load circuit) are connected in series. A constant current circuit 110 supplies the series load circuit with a drive current for the light-emitting unit 851. A current reducing circuit 170 shunts a current, which is equivalent to a difference obtained by subtracting the drive current for the light-emitting element unit 852 from the drive current for the light-emitting element unit 851, from a current flowing in the series load circuit, thereby reducing the current flowing in the light-emitting element unit 852. COPYRIGHT: (C)2010,JPO&INPIT
20 Oct 2009
TL;DR: In this paper, the behavior of the two in tandem fuel cells and ultracapacitors is studied through simulations, and the model is designed to simulate any desired load power profile within the bounds of fuel cell and ultrACapacitor ratings.
Abstract: Fuel cells are ideal candidates for use in hybrid electric vehicles due to their high energy density However the power requirements of these automobiles cannot be satisfied by the slow transient response of fuel cells Ultracapacitors however have high power density and provide good transient characteristics The behavior of the two in tandem is studied through simulations The fuel cell and ultracapacitor are initially sized for the desired load and then the active load sharing between the two is examined The model is designed to simulate any desired load power profile within the bounds of fuel cell and ultracapacitor ratings The purpose of this model is to provide researchers with a fuel cell - ultracapacitor based platform for hybrid electric vehicles
Patent•
3 Feb 2009TL;DR: In this paper, a current mirror circuit and an optical receiver circuit implementing with the current mirror circuits are described, where two MOSFETs and two differential amplifiers are operated under the same bias condition even the power supply voltage decreases due to the virtual short-circuit characteristic between two inputs of the differential amplifier.
Abstract: A current mirror circuit and an optical receiver circuit implementing with the current mirror circuit are disclosed. The current mirror circuit provides two MOSFETs and two differential amplifiers. The MOSFETs are operated under the same bias condition even the power supply voltage decreases due to the virtual short-circuit characteristic between two inputs of the differential amplifier. One of the differential amplifiers provides a variable gain and output impedance characteristic to stabilize the feedback loop formed by this differential amplifier and one of the MOSFETs.
Patent•
10 Nov 2009TL;DR: In this paper, a voltage converter is used to adjust voltage between two levels, and a load resistor is controlled such that the load resistor alternatively taps the latter voltage level to a capacitor or another capacitor of a potentiometer.
Abstract: The arrangement has a voltage converter i.e. capacitor transducer (6), adjusting voltage between two levels. The voltage converter represents a coupling element between the voltage levels and transmits energy from one of the voltage levels to the other voltage level. A load resistor (5) of the arrangement is controlled such that the load resistor alternatively taps the latter voltage level to a capacitor or another capacitor of a potentiometer. The potentiometer is formed as a capacitive potentiometer. The load resistor is controlled by switching devices e.g. change over switches. An independent claim is also included for a main power supply of a motor vehicle.
Patent•
22 Oct 2009
TL;DR: An uninterruptible power supply supporting active loads includes a charge and discharge module having a battery set and a charger charging the battery set with an input power, a switch circuit having at least two active switches connected to the battery, a dynamic PWM control module connected with each of the active switches of the switch circuit, alternately outputting duty cycles composed of low-frequency square wave and high frequency square wave as mentioned in this paper.
Abstract: An uninterruptible power supply supporting active loads includes a charge and discharge module having a battery set and a charger charging the battery set with an input power, a switch circuit having at least two active switches connected to the battery set, a dynamic PWM control module connected with each of the active switches of the switch circuit, alternately outputting duty cycles composed of low-frequency square wave and high-frequency square wave and alternately controlling each of the active switches to turn on or off, and a transformer having a primary side connected with the switch circuit and a secondary side whose two terminals are connected with an output capacitor generating a filtering function in collaboration with an leakage inductor in the secondary side of the transformer. The uninterruptible power supply generates a quasi-continuous output satisfying the hold-up time demanded by an active load.