Abstract: A variable load circuit (2) is provided for use with a dimmer (1). A low wattage load such as a LED (3) is provided in series with the dimmer and the variable load circuit is provided in parallel with the LED. The variable load circuit has two different load characteristics: when the applied voltage from the dimmer is below a threshold, the variable load circuit presents a fixed load (24), and when the applied voltage is above a threshold the variable load circuit presents a variable load so as to act as a constant current sink. The variable load is provided by a secondary load portion (25) which may or may not act in combination with the fixed load (24), and the secondary load portion (25) is switched in or out of the variable load circuit by a trigger circuit portion (26).

Abstract: A switching circuit for supplying current to a load has a switching element, an inductive element coupled to the switching element, and a load current extraction circuit responsive to current in the inductive element for producing a load current signal as a simulated current approximating current in the load.

Abstract: The subject invention provides a photoreceiver/amplifier circuit comprising a differential circuit including a differential transistor pair and a bias circuit; an active load; a feedback resistor for converting a photocurrent generated from a photodiode into a voltage; a reference resistor; and a compensation circuit. The resistance of the feedback resistor is greater than the resistance of the reference resistor. The compensation circuit supplies a compensation current from a junction between the feedback resistor and a non-inverting input terminal of the differential amplifier circuit, so as to cancel the difference between a voltage between terminals of the feedback resistor and a voltage between terminals of the reference resistor. This reduces noise and improves offset voltage characteristics. The present invention provides a photoreceiver/amplifier circuit ensuring noise reduction and desirable offset voltage characteristics.

Abstract: An aircraft load management system that determines the position of an aircraft cargo hook for display to an aircrew. The cargo hook positional information may alternatively or additionally be communicated directly to a flight control system and a winch control system to automate and coordinate flight control inputs with winch operation to actively position the cargo hook. Data transfer from the cargo through a data link system also provides the load management system with exact position of the cargo load connection points even prior to attachment of the cargo hook to the load. The load management system also includes anti-sway algorithms for active load stability inputs to the flight control system and to alter flight control laws and automatically compensate for CG. excursions.

Abstract: It's an object-based storage device load balancing method, belonging to the computer storage technology, aiming at balancing the distribution of the system load in the storage nodes by reasonable scheduling of I / O load and hot data migration, to take full advantage of high-performance of storage device nodes The order of the invention includes: (a) active load detection steps; (2) equipment load statistics steps; (3) object migration and copies management steps; (4) object properties expansion steps; (5) I / O request processing steps The invention expands the SCSI protocol standards of object storage devices (OSD) With the advantages of object storage model, it provides basis for I/O scheduling decision, makes full use of the computing capacity of all the storage nodes to balance the load, reduce storage system response time and increase the storage system throughput

Abstract: A voltage divider circuit generating a divided voltage by dividing an input voltage with a predetermined voltage division ratio, and outputting the divided voltage is disclosed. The voltage divider circuit includes a first resistor circuit including multiple resistors connected in series, the resistors being connected in parallel to corresponding fuses; and a second resistor circuit including multiple resistors connected in series, the resistors being connected in parallel to corresponding fuses, the second resistor circuit being connected in series to the first resistor circuit. The divided voltage is output from the connection of the first resistor circuit and the second resistor circuit, and the fuses of the first resistor circuit and the second resistor circuit are subjected to trimming so that the combined resistance of the first resistor circuit and the second resistor circuit is constant.

Abstract: The voltage source converters VSC's are converters highly used in systems of distributed generation, HVDC's and motor drivers, thanks to the feasibility and facility to control the active and reactive power independently, in a fast and effective way. In this paper the performance of a VSC in its dynamic and steady state behavior is analyzed, where a model is validated in certain operation range and particular conditions; in addition a nonlinear fuzzy control was proposed for controlling independently the active and reactive power flow, between a VSC and an active load, with excellent results.

Abstract: An overcurrent detection circuit for detecting an overcurrent condition in an output transistor connected in series with an electrical load includes a pair of transistors having input terminals connected together. The pair of transistors is interposed between a current mirror circuit and a resistor and between the current mirror circuit and a detection transistor capable of being turned on at the same time as the output transistor. When a voltage is applied to the input terminals of the pair of the transistors, output terminals of the current mirror circuit are fixed at the same potential. Thus, even when an early effect occurs in the current mirror circuit, an electric current flowing through the resistor becomes equal to that flowing through the detection transistor. The overcurrent detection circuit can accurately detect the overcurrent condition based on a voltage drop across the resistor.

Abstract: An electrical stimulation device is for a biological load for applications such as transcutaneous nerve stimulation, neuromuscular electrical stimulation, or electrical muscle stimulation. The device comprises a controller, a power generation circuit for output of power to electrodes. A feedback compensation circuit has a sensor for sensing delivered current in the load and for providing feedback to the power delivery circuit. The feedback compensation components are integrated into the power generation circuit so that only the required power is generated and there is no need to dissipate excess power. Hence there is no need for a current limiting circuit between the power generation circuit and the load. The sensor comprises a sense resistor (Rsense,) in the load and a voltage tap (Vfb) across the sense resistor. The voltage tap is provided as a signal input to an error amplifier (EA) of the feedback compensation circuit, the other input being a reference voltage (Vref) representing a desired load current.

Abstract: This paper presents 50 kVA active load with low loss, which regenerate the power to utility To make the regenerative load, 3 phase back to back inverter using DSP320C33 have been made and tested One inverter control the power flow of the test system and the other control the regeneration of the power to utility It could be used as a nonlinear load, resistive load, and reactive load for single phase AC, DC, three phase AC Also, load step change and unbalanced load is simply implemented by the proposed converter The 50 kW prototype is made and tested to verify the regenerative load function

Abstract: To accelerate the speed of RF power amplifier design, a novel ultra-fast real-time active load-pull measurement based on a large signal network analyzer (LSNA) is presented. Real-time load-pull conventionally uses a single-tone excitation at the transistor's output to achieve a time varying load impedance. However this approach still requires multiple measurements at different power levels to map the Smith Chart and determine the optimal load termination. This paper proposes a modulated two-tone excitation method for mapping the Smith Chart in a single 10 ms LSNA measurement. Experiments for the lst and 2nd harmonic demonstrate that this ultra-fast real-time active load-pull permits to identify the optimal load impedance in one measurement.

Abstract: An AC maintain power signature detection circuit in a power sourcing equipment (PSE) for a Power over Ethernet system injects an AC test signal onto a power port of the PSE. The AC test signal is driven onto a first power terminal of the power port through a sense resistor. The voltages across the sense resistor are measured and scaled by first and second resistor dividers having different resistor ratios. The voltage and the scaled voltage at the first power terminal side of the sense resistor have a peak voltage being proportional to the load impedance of the load coupled to the power port. The comparator compares the scaled voltages measured across the sense resistor and generates the output signal indicative of the load impedance at the power port.

Abstract: In this paper, a wide-range DLL-based frequency multiplier with PMOS active load for communication applications is proposed. Adding the PMOS active load in the delay cells has the inductive-peaking effect to increase the operation frequency range. The DLL-based frequency multiplier uses simple exclusive-or (XOR) gates and phase blending technique for the frequency multiplications. The frequency multiplier can generate N times of frequency of the input clock when the number of delay cells (N) in the VCDL is even. The output frequency of the proposed frequency multiplier ranges from 80MHz to 2.24GHz using TSMC 0.18mum CMOS process. The locked time is 0.96ns locked time at 400MHz. The peak-to-peak jitter is 46ps at 80MHz and 95.3ps at 2.24GHz. The power consumption of proposed frequency multiplier is 25.79mW at 400MHz.

Abstract: Active circuits with active loads linearized via distortion cancellation are described. In one design, an apparatus includes a first stage and a load stage. For an amplifier, the first stage amplifies an input signal and provides an output signal having a larger signal level. For a mixer, the first stage mixes an input signal with an LO signal and provides an output signal. The load stage provides an active load for the first stage and is linearized by canceling distortion generated by the active load. In one design, the load stage includes a first transistor that provides the active load and generates distortion due to its nonlinearity. The load stage further includes at least one transistor that generates a replica of the distortion from the first transistor. The distortion replica is used to cancel the distortion from the first transistor. The first stage may also be linearized with distortion cancellation.

Abstract: A current sense amplifier can include an active load circuit having a first load device and second load device coupled in parallel to a first power supply node. A first load device and second load device can provide an impedance that varies according to a potential at a load control node. A reference current circuit can be coupled between the first load device and a second power supply node that includes a current reference section that provides an impedance according to a bias voltage. A data current circuit can be coupled between the second load device and a plurality of memory cells. An adaptive bias circuit can be coupled between the first power supply and the second power supply node and can include a bias section coupled to the load control node that provides an impedance according to the bias voltage.

Abstract: Embodiments of the invention may provide for a load regulation tuner that reduces the load regulation effect. The load regulation tuner may include a load current controlled current source that is responsive to a load current from a power transistor of a linear regulator, where the load current controlled current source includes a sensing transistor that generates a fraction of the load current as a sensed partial load current. The load regulation tuner may also include a resistor in parallel with a load current controlled current source, and where the paralleled resistor and the load current controlled current source form at least a portion of a feedback block that adjusts an operation of the linear regulator to provide a substantially constant load voltage.

Abstract: A voltage generation circuit comprises a reference voltage generation circuit; a differential amplifier; an output node; a P-channel MOS transistor; a first resistor series; a second resistor series; a third resistor series; and a selection control circuit. A reference voltage generated by the reference voltage generation circuit is input to a first input terminal of the differential amplifier. The first resistor series is connected between a drain of the P-channel MOS transistor and the output node. The second resistor series is connected between the output node and a second input terminal of the differential amplifier. The third resistor array is connected between the second input terminal of the differential amplifier and a ground. The selection control circuit controls such that a sum of the resistances of the first resistor series and the second resistor series is constant

Abstract: This paper presents a new linearity improvement technique for a CMOS active resistor. In order to minimize the silicon occupied area, an original method will be designed, having the result of about two order of magnitude reducing area with respect to a classical resistor. The circuit theoretical estimated linearity error is 0.35% for an input range of ±500mV, confirmed by SPICE simulations. The circuit is designed for low-voltage low-power application (a supply voltage of about ±3.3V) and it is implemented in 0.35μm CMOS technology. The layout area (60μm x 80μm) is minimized using an original technique based on an optimal implementation of the current-controlled voltage generators from the active resistor circuit.

Abstract: A current supply includes a current mirror arrangement having a feedback circuit. The current supply includes a current mirror input stage connected to a constant current source providing a reference current; a current mirror output stage providing an output current substantially mirroring the reference current; and a feedback circuit feeding back to the current mirror input stage a feedback signal representing perturbations in the output current to cause the output current to more accurately mirror the reference current. In one embodiment, a dummy current mirror output stage substantially mirrors the reference current, and the feedback circuit receives a signal from the dummy current mirror output stage, and in response thereto, supplies the feedback signal to the current mirror input stage to cause the output current to more accurately mirror the reference current.

Abstract: Load modeling is very important for power system dynamic analysis and control. The composite load model widely applied recently in the power system operation centre consists of the static load and the equivalent motor. Current practices in measurement-based load modeling identify all the parameters in this composite load model. However, it is not clear whether all these parameters could be identified from the measurements. This paper investigates the identifiability of the equivalent motor parameters in the composite load model. Trajectory sensitivity approach is applied first to find the motor parameters that have great effects on the measured active as well as reactive load dynamics. The analysis results show that the motor outputs have various sensitivities with respect to the parameters. Since the voltage disturbance, the active load and the reactive load dynamics are applied to identify the motor parameters, those parameters affecting the measurements to a great extent are observable, thus identifiable from the measurements; while those that have little effects on the motor outputs are unobservable from the measurements and consequently unidentifiable. The case studies verify the identifiability of the motor parameters.

Abstract: A signal conditioning circuit for a latching comparator comprising first and second transistors arranged in a long tail pair, the long tail pair having an active load and configured to act as an integrator.

Abstract: A binary bidirectional trimming circuit is disclosed. The trimming circuit includes: a first resistor set having 4 resistors in parallel connected and a first fuse bridged two ends thereto provide one trimming step; a second resistor set having 2 resistors in series connected and a second fuse bridged two ends thereto provide eight trimming steps; a third resistor set having 2 resistors in parallel connected and a third fuse bridged two ends thereto provide two trimming steps; a fourth resistor set having 1 resistor and a fourth fuse bridged two ends thereto provide four trimming steps; a first loading resistor; and a second loading resistor. The first resistor set, second resistor set, first loading resistor, third resistor set, the fourth resistor set, and the second loading resistor are in series connected. The output terminal is located at the nodes of the third resistor set and the first loading resistor so that the trimming steps provided by the third resistor set and the fourth resistor set are opposite to that of the first resistor set and the second resistor set.

Abstract: A voltage generation circuit may include a static current circuit and/or a current mirror. The static current circuit may include a first resistor. The current mirror may include a second resistor, a third resistor, and/or an output terminal.

Abstract: The width dependence to the interfacial effect of mis-matching characteristics of a boron doped non-silicided polysilicon resistor has been studied The fundamental properties for using P+ poly resistor in the integrated circuit(IC) design are better linearity and higher unit square sheet resistance Typically, the square resistance of a boron doped non-silicided poly-silicon resistors is 30 times higher than the one of a silicided poly-silicon resistor By using the 018 mum CMOS fabrication technology, the boron doped P+-poly-silicon resistor is built in this paper Based on a simple and useful empirical model, the equivalent circuit parameters of the P+ poly-silicon resistor that include bulk sheet resistance (Rs), interface resistance (Rinterface) silicide resistance (Rinterface) and contact resistance (Rc) are obtained as described in the research on references The references' study already showed that the Rs and Rinterface values are increased with the decrease of resistor width and are decreased with the increase of temperature, respectively However, most of analog related designs, such as ADC (analog to digital converter) and DAC (digital to analog converter) have to use the resistor with large device size in the integrated circuit design for obtaining better circuit performance such as resolution and accuracy during signal conversion This research is firstly to disclose the P+-poly resistor mis-matching effects by distinguishing the role of each equivalent circuit parameters, and explain the limiting factor to use P+-poly silicon resistor in terms of device sizes, such as width and length, and provide a minimum size of P+ poly resistor to use for the circuit designer Besides focusing on the dimension variation for the width and length of the resistor to mis-matching performance, the interface effect of the P+-poly-silicon resistor itself is demonstrated 60% higher than the other effect for the study of this work

Abstract: It is demonstrated that drift-diffusion simulation is a powerful tool in design, optimization and verification of organic circuits. Starting from the simulation of single transistor structures, we treat inverter circuits with active load under both static and transient conditions while analyzing the effects of different transistor geometries. Never shown before, a dynamic finite element simulation of a full three-stage organic ring oscillator operating at 105 kHz is presented.

Abstract: The excessive unbalanced current in the network cause voltage distortion, excessive flow of neutral current, heating of electrical machines, transformers and poor power factor in the most primitive form of load compensation. The load compensation based on application of active power filter for symmetrical component theory is much simpler than p-q theory. It does not require complex transformations of currents and can effectively control the unbalanced load currents. The application of active power filter based on symmetrical component theory used for six different cases and the load compensation results obtained through MATLAB programming.

Abstract: The energy function method developed so far assumes that the active load is constant. However, most of the actual load is voltage dependent, which hinders the application of the energy analysis method to the actual power system. On the other hand, the fast development of measurement techniques, especially the wide area measurement systems (WAMS) applied widely in worldwide power system nowadays, presses for the on-line transient stability analysis tools based on the system measurements. The voltage-dependent load into the energy analysis of power system transient stability is discussed. The effect of the comprehensive load characteristics on the system energy is discussed and a WAMS-based energy indicator on the system stability status is proposed. The indicator is easy to be calculated and thus real-time in the operation centre is monitored. The proposed method does not rely on any specific load model, and various load characteristics on different buses can be considered. Simulations on two test systems verify the effectiveness of the proposed method.

Abstract: A circuit (240) comprises an inductive load (230). The circuit (240) further comprises an energy-absorbing component operably coupled to the inductive load (23) and arranged to absorb energy generated by the inductive load (230).

Abstract: In the electric power system, grasping active and reactive load variation regularity of each node is a key for optimal dispatch, preventive control, security assessment, and transmission capacity evaluation, etc This paper presents an approach of ultra-short forecasting for multi-node active and reactive load on the basis of former researches It proposes a hierarchy and subarea idea to construct a framework of self- adapting dynamic model With the top layer load forecasting implemented by recursive least square support vector machines (RLS-SVM) algorithm, discrete state-space equations are established to describe dynamic characteristics of multi-node load parameters (active load distribution factors and power factors), and then TS fuzzy control technique is introduced to realize feedback compensation The application in an actual power system control center of Shandong province has been verified with satisfactory result