ACCESS.bus

Abstract: An simulation device of bus arbitration is prepared as adding a bus arbitrator in simulation model of ARMulator to let operation of access bus on all bus master units including ARM Core pass arbitration of said bus arbitrator first, enabling to make access on bus slave unit and to obtain required return-back value only after bus is obtained

Abstract: The invention relates to a multi-main-bus arbitration sharing device, which comprises a first processor, a second processor, a complex programmable logic device (CPLD), a chip-select-line read-write-line drive device and a motherboard comprising multiple data buses, wherein after receiving a request bus event of the first and the second processors, the CPLD arbitrates the request bus event and returns an arbitration result to the first and the second processors; a processor obtaining an access priority transmits an access bus event to the CPLD; after the CPLD receives the access bus event, the access bus event is transmitted by the chip-select-line write-read-line drive device to the motherboard; after receiving the access bus event, the motherboard executes the write or read operation on the bus; after the access of the processor obtaining the access priority is ended, the bus access ending event is returned by the motherboard to the processor through the CPLD; and the processor obtaining the access priority executes the write or the read operation according to the bus access ending event so as to complete the multi-main-bus arbitration sharing operation.

Abstract: PURPOSE:To shorten the waiting time of a bus and to improve the performance of a processor unit by forming a directory memory access bus contention circuit to provide priority to a bus using request from the processor unit. CONSTITUTION:When a bus using request is generated from the processor unit 13, a bus using permission signal is turned to ''1'' through an AND gate, a J- KFF, etc. in the direct memory access (DMA) bus contention circuit 15 to permit the use of the bus. Even if an I/O 17 or the like outputs a bus using request signal, the bus can not be used until the unit 13 ends the use of the bus. If a bus using request is outputted from the unit 13 again even when the bus using by the unit 13 has been ended and the bus is being used by the I/O 17 or the like, the bus using request from the unit 13 is made prior to other unit. consequently, the bus waiting time can be shortened and the performance of the processor unit 13 can be improved.

Abstract: Data communication stations 10, 12, 14 are connected by way of a shared bus 15 common to all the communication stations. When two stations attempt to access the shared bus simultaneously, a conflict resolution method if used to determine which of the two stations is allowed access to the bus 15. Each station seeking access to the bus 15 serially transmits its address. The priority of the stations is determined, and the station with priority is given access to the bus 15.