8-bit

Abstract: This paper presents new speed records for 128-bit secure elliptic-curve Diffie---Hellman key-exchange software on three different popular microcontroller architectures. We consider a 255-bit curve proposed by Bernstein known as Curve25519, which has also been adopted by the IETF. We optimize the X25519 key-exchange protocol proposed by Bernstein in 2006 for AVR ATmega 8-bit microcontrollers, MSP430X 16-bit microcontrollers, and for ARM Cortex-M0 32-bit microcontrollers. Our software for the AVR takes only 13,900,397 cycles for the computation of a Diffie---Hellman shared secret, and is the first to perform this computation in less than a second if clocked at 16 MHz for a security level of 128 bits. Our MSP430X software computes a shared secret in 5,301,792 cycles on MSP430X microcontrollers that have a 32-bit hardware multiplier and in 7,933,296 cycles on MSP430X microcontrollers that have a 16-bit multiplier. It thus outperforms previous constant-time ECDH software at the 128-bit security level on the MSP430X by more than a factor of 1.2 and 1.15, respectively. Our implementation on the Cortex-M0 runs in only 3,589,850 cycles and outperforms previous 128-bit secure ECDH software by a factor of 3.

Abstract: A pipelined 8-bit-serial single-flux-quantum (SFQ) microprocessor, called CORE1beta, was designed and tested. The CORE1beta has two cascaded arithmetic logic units (ALUs) based on forwarding architecture, which can perform two register operations from one instruction. Pipelining is also extensively adopted to enhance the performance. A new design method, known as one-hot encoding, has been introduced into the design of the control circuit. The 4-stage-pipelined SFQ microprocessors, CORE1beta8, have been implemented using the CONNECT cell library and the SRL 2.5 kA/cm2 Nb process. The frequency for the instruction fetch is 25 GHz, and 20 GHz for the bit-serial data operation. The peak performance and the power consumption of the CORE1beta8 are estimated to be 1400 MOPS (million instructions per second) and 3.4 mW, respectively. We have experimentally demonstrated 4-stage pipelining and all functionalities of the CORE1beta8 microprocessors by on-chip high-speed tests.

Abstract: TITAC is an asynchronous version of an 8-bit von Neumann microprocessor based on the delay-insensitive model incorporating the isochronic-forks assumption. In its two-phase, event-driven design scheme, a working phase and an idle phase alternate to execute control and data transfer. The data path design uses a two-rail, multilevel AND-OR scheme with a binary decision diagram structure for efficient signal generation. >

Abstract: A description is given of the CLIP7 image-processing chip. The device is implemented as a custom designed integrated circuit and contains a single processing element for use in arrays of processors. The chip uses 16-bit internal and 8-bit external data buses and divides crudely into two major sections: data processing and data input/output. The first structure to be assembled using these processors is a 256-element linear array, each element incorporating two of the CLIP7 processors. This system, known as CLIP7A, is used both to study the application of partial local autonomy techniques to image processing and also as a fast and convenient system for the emulation of other architectures. CLIP7A software and hardware are also described. >