64b/66b encoding

Abstract: In a more effective data generation method and circuit used for 64B/66B encoding, when packet data, and head and tail information of the data packet are received, write user data in which a head and tail identifying bytes are respectively added to a head and a tail of the packet data based on the head and tail information is associated with control data indicating positions of both of the identifying bytes to be written in a memory sequentially from a predetermined address of the memory. From the predetermined address, user data by 8 bytes and the control data corresponding to the user data are sequentially read to be provided to a 64B/66B encoding circuit. During a period in which the reading can not be made, idle bytes for 8n bytes (n≧1) and control data indicating the idle bytes, or maintenance user data of 8n bytes (n≧2) in which the head and tail identifying bytes are respectively added to a head and a tail of the maintenance information and control data indicating positions of both of the identifying bytes are provided to the 64B/66B encoding circuit.

Abstract: With the emergence of new high-speed data standards, such as the IEEE 802.3ba, the clock rate on individual channels can go up to 10 Gbps creating the need for highly efficient encoding schemes. One such scheme is the 64b/66b. An undesired effect of using encoding schemes is the spreading of signal power to higher harmonics, thereby requiring greater bandwidth to transmit the signal. A clear understanding of the exact effect of the encoding scheme on the PSD of the transmitted data will help in better understanding the bandwidth requirements associated with these encoding schemes. This will prevent over budgeting of the channel requirements and allow for more exact specifications to be developed. This paper analyzes the change in the power spectral density of random data when encoded using 64b/66b scheme. A comparison to similar effects caused by using 8b/10b is presented for reference. The results show consistent variations in PSD which allow us to characterize the encoding scheme.

Abstract: The present invention provides a test apparatus for a 64B/66B encoding process capable of precisely performing a test with a high reproducibility on a certain pattern of a 64B/66B encoder or decoder. A frame generator generates frame data in a layer higher than a physical coding sublayer of Ethernet (registered trademark) and inputs the frame data to a 64B/66B encoder such that the 64B/66B encoder performs a 64B/66B encoding process of the physical coding sublayer with respect to the frame data. A sequence pattern generator generates a certain 66B sequence pattern written in advance, and a controller writes a desired sequence pattern in the sequence pattern generator and, at the same time, controls a data selector to select one of data encoded by the 64B/66B encoder and a sequence pattern output from the sequence pattern generator and to provide the selected one to a test subject.

Abstract: PROBLEM TO BE SOLVED: To accurately perform test of an arbitrary pattern to a 64B/66B encoding or decoding, with high reproducibility. SOLUTION: Frame data at a level higher than a physical coding sublayer of the Ethernet (R) is generated from a frame generator 21 and is then input to a 64B/66B encoder 22 for 64B/66B encoding operation of the physical coding sublayer. Meanwhile, a sequence pattern generator 23 generates an arbitrary 66B sequence pattern previously written. A controller 50 writes a desired sequence pattern in the sequence pattern generator 23 and selects either the data encoded by a 64B/66B encoder 22 or a sequence pattern issued from the sequence pattern generator 23 and imparts the one selected to a test target device by controlling a data selector 24. COPYRIGHT: (C)2010,JPO&INPIT