Topic
31-bit
About: 31-bit is a research topic. Over the lifetime, 4 publications have been published within this topic receiving 28 citations.
Papers
Patent•
IBM1
TL;DR: In this paper, an apparatus is presented and proved for detecting storage operand overlap for instructions having identical overlap detection requirements as the move character (MVC) instruction, which is applicable to all Enterprise Systems Architecture (ESA)/390 addressing modes encompassing access register addressing for either 24 bit or 31 bit addressing.
Abstract: An apparatus is presented and proved for detecting storage operand overlap for instructions having identical overlap detection requirements as the move character (MVC) instruction. The apparatus is applicable to all Enterprise Systems Architecture (ESA)/390 addressing modes encompassing access register addressing for either 24 bit or 31 bit addressing. S/370 addressing in 24 bit and 31 bit modes are also supported by the proposed apparatus and treated as special cases of access register addressing. In addition, the apparatus is extended to support other addressing modes with an example provided to include a 64 bit addressing mode. A fast parallel implementation of the apparatus is also presented. The apparatus results in a one cycle savings for all invocations of the MVC instruction which comprises approximately 2% of the dynamic instruction stream of a representative instruction mix. The one cycle savings results in a 21 percent improvement in the performance of the execution of the MVC instruction for the frequent case (84%) when the operand length is less than or equal to eight bytes and a 9 percent improvement in performance for the less frequent case (16%) in which the operand length is greater than eight bytes.
13 citations
Patent•
IBM1
TL;DR: In this article, a millicode instruction loads a address extension register with extended address bits, and an operand access control register that signals when a logical address is to be extended by the extra bits and when it should be treated as only a 31 bit address.
Abstract: A millicode instruction loads a millicode address extension register with extended address bits, and an operand access control register that signals when a logical address is to be extended by the extra bits, and when it should be treated as only a 31 bit address.
9 citations
Patent•
IBM1
TL;DR: In this article, a millicode instruction loads a address extension register with extended address bits and an operand access control register that signals when a logical address is to be extended by the extra bits, and when it should be treated as only a 31 bit address.
Abstract: A millicode instruction loads a millicode address extension register with extended address bits, and an operand access control register that signals when a logical address is to be extended by the extra bits, and when it should be treated as only a 31 bit address
6 citations
Patent•
IBM1
TL;DR: In this paper, a method, system and computer-usable medium are disclosed for performing a network traffic combination operation, a plurality of input queues are defined by an operating system for an adapter based upon workload type (e.g., as determined by a transport layer).
Abstract: A method, system and computer-usable medium are disclosed for performing a network traffic combination operation. With the network traffic combination operation, a plurality of input queues are defined by an operating system for an adapter based upon workload type (e.g., as determined by a transport layer). Additionally, the operating system defines each input queue to match a virtual memory architecture of the transport layer (e.g., one input queue is defined as 31 bit and other input queue is defined as 64 bit). When data is received off the wire as inbound data from a physical NIC, the network adapter associates the inbound data with the appropriate memory type. Thus, data copies are eliminated and memory consumption and associated storage management operations are reduced for the smaller bit architecture communications while allowing the operating system to continue executing in a larger bit architecture configuration,
Performance Metrics
| Year | Papers |
|---|---|
| 2015 | 1 |
| 1997 | 1 |
| 1995 | 1 |
| 1992 | 1 |