2B1Q

Abstract: The range of digital data communication services, such as a basic rate 2B1Q ISDN channel, to customer premises located beyond the industry standard achievable range of a two-wire loop can be extended by increasing the capacity of the ISDN line code from two information bits per symbol to three information bits per symbol, so as to reduce the effective symbol rate, which is error correction encoded to an effective 4B1H line code for defining a sixteen level PAM signal waveform, and employing enhanced low signal-to-noise ratio signal processing techniques in both the transmitter and receiver to accommodate the increased insertion loss of the two-wire line resulting from its extended length. Such enhanced low signal-to-noise ratio signal processing techniques include a Tomlinson precoder in the transmitter, and an adaptive linear equalizer and a module unit in the receiver.

Abstract: A digital subscriber loop interface unit, connected to a digital subscriber loop, includes an echo canceler for carrying out a echo canceling operation, a decision feedback equalizer for carrying out an equalizing operation, and a transversal filter, provided in at least one of the echo canceler and the decision feedback equalizer, in which a plurality of taps among all taps are grouped into groups, each group including a predetermined number of taps continuously arranged, a single tap coefficient being assigned to the taps in each group. A digital subscriber loop interface unit may include an echo canceler for carrying out a echo canceling operation by using a value obtained by adding +1 to a symbol value represented by a 2B1Q code. Further, the echo canceler may have a jitter echo canceler in which a convolution operation is carried out by using a value obtained by adding +1 to a symbol value represented by the 2B1Q code, the tap coefficient used in the convolution operation is changed in accordance with a time elapsing from occurrence of the jitter. Furthermore, a digital subscriber loop interface unit may have a low-pass filter in which a filter coefficient is changed based on whether the decision feedback equalizer is in or after a pull-in step.

Abstract: A variety of signal processing techniques have been developed over the past 10 years to increase the bit rate of digital transmission through telephone loop twisted pairs. The ISDN basic rate access 2B1Q digital subscriber line (DSL) was the first technology of this type to be deployed commercially at 160 kb/s full-duplex transmission on a single twisted pair. Other transmitter/receiver circuits have been developed over the years that support symmetric and asymmetric data transmission from several hundreds of kilobits per second to several megabits per second using the 2B1Q line code in the case of HDSL and various modulation techniques (QAM, CAP, and DMT) in the case of ADSL. These more recent forms of xDSL circuitry have begun to be used to provide commercial Internet access. This article analyzes the system level considerations for using these technologies in the increasing complex loop network of telephone companies. A "next generation" of xDSL access system is proposed, and the requirements for such a system are discussed.

Abstract: Careful partitioning of signal-processing tasks between the analog and digital domains to exploit the strengths of each results in an efficient design of a 2B1Q ISDN basic-rate U-interface single-chip transceiver. This 5-V CMOS device provides transmission across the digital subscriber line at 160 kb/s full duplex, in full compliance with ANSI standard T1.601. The serial 2B+D data from the digital interface is rate-adapted to 160 kb/s and cyclic redundancy check (CRC), maintenance, and control bits are inserted in the digital interface (DIF) section of the circuit. The resulting data stream is then scrambled and 18-b synchronization words are inserted. Conversion to an 80-kHz four-level signal takes place in the line encoder. The transmitter includes a 2B1Q pulse shaper, a five-level fully differential pulse-duration-modulation digital-to-analog (PDM D/A) converter, a third-order transmit filter, and a fully differential line driver. A raised-cosine 78% time-roll-off pulse is stored in the pulse shaper, using a PDM code, at 96 samples per baud. Pulse symmetry allows storage of the first half-pulse only. The back half is generated by a time-mirror circuit. At every baud interval, the current di-bit encodes the pulse front half, while the past di-bit encodes the pulse back half. The two resulting quantities are then combined and provided to a 7.68-MHz five-level PDM D/A converter. Undesirable high-frequency components are eliminated by one pole of low-pass filtering in the D/A converter circuit and two extra poles in the line drive circuit. >