Proceedings Article10.1145/266021.266291
Wire segmenting for improved buffer insertion
Charles J. Alpert,Anirudh Devgan +1 more
- 13 Jun 1997
- pp 588-593
TL;DR: Weshow that using wire segmenting as a precursor to buffer insertion produces solutions within a few percent of optimal, while using only seconds of CPU time is shown.
read more
Abstract: Buffer insertion seeks to place buffers on the wires of a signal netto minimize delay. Van Ginneken [Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay] proposed an optimal dynamicprogramming solution (with extensions proposed by [7] [8][9] [12]) such that at most one buffer can be placed on a singlewire. This constraint can hurt solution quality, but it may be circumventedby dividing each wire into multiple smaller segments.This work studies the problem of finding the correct number of segmentsfor each wire in the routing tree. Too few segments yieldssub-par solutions, but too many segments can lead to excessive runtimes and memory loads. We derive new theoretical results forcomputing the appropriate number of buffers (and hence wire segments)which motivate our new wire segmenting algorithm. Weshow that using wire segmenting as a precursor to buffer insertionproduces solutions within a few percent of optimal, while usingonly seconds of CPU time.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
•Book
On-Chip Communication Architectures: System on Chip Interconnect
Sudeep Pasricha,Nikil Dutt +1 more
- 01 Jan 2008
TL;DR: This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design, and will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on- chip communication architectures.
267
•Book
Electronic Design Automation: Synthesis, Verification, and Test
Laung-Terng Wang,Yao-Wen Chang,Kwang-Ting Cheng +2 more
- 11 Mar 2009
TL;DR: EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits.
250
Equivalent Elmore delay for RLC trees
TL;DR: Closed-form solutions for the 50% delay, rise time, overshoots, and settling time of signals in an RLC tree are presented and have significantly improved accuracy as compared to the Elmore delay for an overdamped response.
199
Buffer block planning for interconnect-driven floorplanning
Jason Cong,Tianming Kong,David Z. Pan +2 more
- 07 Nov 1999
TL;DR: An effective buffer block planning (BBP) algorithm is developed to perform buffer clustering such that the overall chip area and the buffer block number can be minimized.
Equivalent Elmore delay for RLC trees
Yehea Ismail,Eby G. Friedman,Jose L. Neves +2 more
- 01 Jun 1999
TL;DR: Closed form solutions for the 50% delay, rise time, overshoots, and settling time of signals in an RLC tree are presented, which have the same accuracy characteristics as the Elmore delay model for RC trees and preserves the simplicity and recursive characteristics of theElmore delay.
References
The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers
TL;DR: It is found possible to define delay time and rise time in such a way that these quantities can be computed very simply from the Laplace system function of the network.
1.7K
Buffer placement in distributed RC-tree networks for minimal Elmore delay
L.P.P.P. van Ginneken
- 01 May 1990
TL;DR: An algorithm is presented for choosing the buffer positions for a wiring tree such that the Elmore delay is minimal, and an extension of the basic algorithm allows minimization of the number of buffers as a secondary objective.
543
CMOS Circuit Speed and Buffer Optimization
N. Hedenstierna,Kjell Jeppson +1 more
TL;DR: An improved timing model for CMOS combinational logic is presented, which yields a better understanding of the switching behavior of the CMOS inverter than the step-response model by considering the slope of the input waveform.
467
Optimal wire sizing and buffer insertion for low power and a generalized delay model
TL;DR: This approach represents the first work on buffer insertion to incorporate signal slew into the delay model while guaranteeing optimality and efficiently computes the complete, optimal power-delay trade-off curve for added design flexibility.
305
Optimum buffer circuits for driving long uniform lines
Sanjay Dhar,Mark A. Franklin +1 more
TL;DR: The design of optimum buffer circuits for driving long uniform lines is discussed, and it is shown that accepting a small increase in delay can lead to a significant decrease in the area occupied by the buffers.
156