Wave Pipelining using Self Reset Logic

TL;DR: These results demonstrate that cost-effective automation systems can successfully control substrate water content for each plant, to accurately compare their phenotypic responses to drought, and be scaled up for high-throughput phenotyping studies.

TL;DR: A novel design approach combining Wave Pipelining and Self Reset Logic provides an elegant solution at high speed data throughput with significant savings in power and area as compared with other dynamic CMOS Logic implementations.

TL;DR: A low power Viterbi decoder is designed in circuit level using self reset logic and wave pipelining technique is implemented for high speed operation and the result shows the power consumption is reduced and the speed of the circuit is increased.

TL;DR: The present design provides an effective input isolation/decoupling circuit technique that allows the input pulse widths to vary over a wide range, resulting in an effectiveinput isolation scheme.

TL;DR: An approach that extends static timing analysis to a high-performance dynamic CMOS logic family called self-resetting CMOS (SRCMOS) and develops an SRCMos timing analyzer implemented as extensions to a standard static timingAnalysis program, thus facilitating its integration into an existing design system and methodology.

TL;DR: This circuit combines a sum-addressed-memory (SAM) cache with delayed-reset logic circuitry, enabling cache access with a two-cycle-latency for a 6OO MHz third-generation superscalar processor implementing the Sparc V9 64b architecture.

TL;DR: In this paper, the authors describe an approach that extends static timing analysis to a high-performance dynamic CMOS logic family called self-fresetting CMOS (SRCMOS) and define various macrolevel timing tests which ensure that fundamental gate-level timing constraints are satisfied.