Journal Article10.1109/TCOMM.2003.809247
VLSI architectures for the MAP algorithm
TL;DR: It is shown that the critical path of the algorithm can be reduced if the add-MAX* operation is reordered into an offset-add-compare-select operation by adjusting the location of registers.
read more
Abstract: This paper presents several techniques for the very large-scale integration (VLSI) implementation of the maximum a posteriori (MAP) algorithm. In general, knowledge about the implementation of the Viterbi (1967) algorithm can be applied to the MAP algorithm. Bounds are derived for the dynamic range of the state metrics which enable the designer to optimize the word length. The computational kernel of the algorithm is the add-MAX* operation, which is the add-compare-select operation of the Viterbi algorithm with an added offset. We show that the critical path of the algorithm can be reduced if the add-MAX* operation is reordered into an offset-add-compare-select operation by adjusting the location of registers. A general scheduling for the MAP algorithm is presented which gives the tradeoffs between computational complexity, latency, and memory size. Some of these architectures eliminate the need for RAM blocks with unusual form factors or can replace the RAM with registers. These architectures are suited to VLSI implementation of turbo decoders.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Hidden semi-Markov models
TL;DR: An overview of HSMMs is presented, including modelling, inference, estimation, implementation and applications, which has been applied in thirty scientific and engineering areas, including speech recognition/synthesis, human activity recognition/prediction, handwriting recognition, functional MRI brain mapping, and network anomaly detection.
864
Turbo Equalization: An Overview
Michael Tüchler,Andrew C. Singer +1 more
TL;DR: The turbo equalization approach to coded data transmission over ISI channels is reviewed, with an emphasis on the basic ideas, some of the practical details, and many of the research directions that have arisen from this offshoot, introduced by Douillard, of the original turbo decoding algorithm.
Iterative Decoding of Concatenated Convolutional Codes: Implementation Issues The speed of decoding can be increased by raising the decoder clock frequency, increasing the use of parallel hardware, and judiciously limiting the number of decoding iterations.
Emmanuel Boutillon,Catherine Douillard,Guido Montorsi +2 more
- 01 Jan 2007
TL;DR: It is shown that very efficient parallel architectures are available for all types of turbo decoders allowing high-speed implementations and an evaluation of the complexities of the turbo decmoders as a function of the main parameters of the code is performed.
83
A 2.15GBit/s turbo code decoder for LTE advanced base station applications
Thomas Ilnseher,Frank Kienle,Christian Weis,Norbert Wehn +3 more
- 08 Oct 2012
TL;DR: This work presents the first LTE advanced compliant LTE turbo code decoder with a throughput of 2.15GBit/s at frequency of 450MHz and area of 7.7mm2 in a 65nm process node with worst case P&R constraints.
58
FPGA Implementation of an Iterative Receiver for MIMO-OFDM Systems
TL;DR: An architecture of MMSE iterative receiver for MIMO-OFDM systems is proposed to limit latency and complexity due to iterative process: MMSE equalization implementation is realized using CORDIC operators and specific interleaving functions are introduced to reduce latency and accelerate the convergence process.
55
References
Error bounds for convolutional codes and an asymptotically optimum decoding algorithm
TL;DR: The upper bound is obtained for a specific probabilistic nonsequential decoding algorithm which is shown to be asymptotically optimum for rates above R_{0} and whose performance bears certain similarities to that of sequential decoding algorithms.
7.6K
•Journal Article
Optimal decoding of linear codes for minimizing symbol error rate
TL;DR: The general problem of estimating the a posteriori probabilities of the states and transitions of Markov source observed through a discrete memoryless channel is considered.
6.8K
The viterbi algorithm
Jr. G.D. Forney
- 01 Mar 1973
TL;DR: This paper gives a tutorial exposition of the Viterbi algorithm and of how it is implemented and analyzed, and increasing use of the algorithm in a widening variety of areas is foreseen.
6.5K
Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1
Claude Berrou,A. Glavieux,Punya Thitimajshima +2 more
- 23 May 1993
TL;DR: In this article, a new class of convolutional codes called turbo-codes, whose performances in terms of bit error rate (BER) are close to the Shannon limit, is discussed.
Near Shannon limit error-correcting coding and decoding
Claude Berrou
- 01 Jan 1993
TL;DR: A new class of convolutional codes called turbo-codes, whose performances in terms of bit error rate (BER) are close to the Shannon limit, is discussed.
5.5K