Virtual Compression through Test Vector Stitching for Scan Based Designs
Wenjing Rao,Alex Orailoglu +1 more
- 03 Mar 2003
- pp 10104-10109
TL;DR: A technique for compressing test vectors is proposed that reduces test application time and tester memory requirements by utilizing part of the predecessor response in constructing the subsequent test vector.
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Abstract: We propose a technique for compressing test vectors. The technique reduces test application time and tester memory requirements by utilizing part of the predecessor response in constructing the subsequent test vector. An algorithm is provided for stitching test vectors that retains full fault coverage while appreciably reducing time and tester requirements. The analysis provided enables significant compression ratios, while necessitating no hardware outlay whatsoever, making the technique we propose particularly suitable for SOC testing. The test time benefits necessitate no MISR utilization, ensuring no consequent aliasing loss. We examine a number of implementation considerations for the new compression technique and we provide experimental data that can be used to guide an eventual commercial implementation. Experimental data confirms the significant test application time and tester memory reductions.
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Citations
Test application time and volume compression through seed overlapping
Wenjing Rao,I. Bayraktaroglu,Alex Orailoglu +2 more
- 02 Jun 2003
TL;DR: This paper proposes an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement, and introduces modified ATPG algorithms upon the previous SCC scheme.
Trimodal Scan-Based Test Paradigm
TL;DR: The experimental results obtained for large and complex industrial application-specific IC designs illustrate the feasibility of the proposed test scheme despite additional costs and efforts entailed in consolidating architectural changes and operations across a DFT flow.
39
Putting wasted clock cycles to use: Enhancing fortuitous cell-aware fault detection with scan shift capture
Fanchen Zhang,Daphne Hwong,Yi Sun,Allison Garcia,Soha Alhelaly,Geoff Shofner,LeRoy Winemberg,Jennifer Dworak +7 more
- 01 Nov 2016
TL;DR: The ability of the intervening shift cycles to achieve high static cell-aware fault coverage using only the test patterns generated to detect stuck-at faults is investigated and the number of shadow flops required is investigated.
37
Staggered ATPG with capture-per-cycle observation test points
Yingdi Liu,Janusz Rajski,Sudhakar M. Reddy,Jedrzej Solecki,Jerzy Tyszer +4 more
- 22 Apr 2018
TL;DR: Experimental results obtained for large industrial designs illustrate feasibility of the proposed ATPG, and it appears that original scan cells of a design can provide good observability for staggered test patterns.
22
Test Pattern Compression Based on Pattern Overlapping
Jiri Jenicek,Ondrej Novak +1 more
- 11 Apr 2007
TL;DR: Improvements that have been done on the test pattern compaction and compression algorithm called COMPAS, which is capable to compress data generated by concurrently working ATPG processes, are reported here.
18
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Reducing test application time for full scan embedded cores
Ilker Hamzaoglu,Janak H. Patel +1 more
- 15 Jun 1999
TL;DR: In this article, the authors proposed a parallel serial full scan (PSFS) technique for reducing the test application time for full scan embedded cores, which divides the scan chain into multiple partitions and shifts in the same vector to each scan chain through a single scan in input.
356
Reducing test application time for full scan embeded cores
I. Hamzaoglu
- 01 Jan 1999
TL;DR: A new design for testability technique, Parallel Serial Full Scan (PSFS), for reducing the test application time for full scan embedded cores by dividing the scan chain into multiple partitions and shifting in the same vector to each scan chain through a single scan in input.
331
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
Hyung Ki Lee,Dong Sam Ha +1 more
TL;DR: HOPE as mentioned in this paper is an efficient parallel fault simulator for synchronous sequential circuits that employs the parallel version of the single fault propagation technique, which is based on an earlier fault simulator railed PROOFS, which employs several heuristics to efficiently drop faults and to avoid simulation of many inactive faults.
313
Test volume and application time reduction through scan chain concealment
I. Bayraktaroglu,Alex Orailoglu +1 more
- 22 Jun 2001
TL;DR: A test pattern compression scheme is proposed in order to reduce test data volume and application time and increase the number of scan chains that can be supported by an ATE by utilizing an on-chip decompressor.