Patent
Vertically isolated complementary transistor structures
Abernathey John Robert,Charles W. Koburger +1 more
- 17 Jan 1986
4
TL;DR: In this article, a backfilled cavity was used to prevent the creation of oarasitic channels in complementary transistor devices, where the dopants in the first and second layers outdiffuse into the epitaxial layer and into the backfill material, respectively.
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Abstract: A process for making complementary transistor devices - (11, 12) in an epitaxial layer (14) of a first conductivity type having a deep vertical isolation sidewall (21) between the N and P channel transistors by providing a backfilled cavity - (26) in the epitaxial layer, the sidewalls of the cavity being coated with layers of material, the first layer being a silicate doped with the same conductivity type as the epitaxial layer (14) and in contact with the epitaxial layer. The first layer is overcoated with an isolation and diffusion barrier layer (21). A second silicate layer is provided which is doped to a conductivity opposite to that of the first layer and isolated therefrom by said isolation and diffusion barrier material (21). The cavity (26) is backfilled with semiconductor material of a conductivity type opposite to that of the epitaxial layer (14) and during this backfilling operation the dopants in the first and second layer outdiffuse into the epitaxial layer and into the backfill material, respectively, to prevent the creation of oarasitic channels.
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Citations
Patent
Sidewall spacers for cmos circuits stress relief/isolation and method for making
Anthony John Dally,Ogura Seiki,Jacob Riseman,Nivo Rovedo +3 more
- 23 Jan 1987
TL;DR: In this paper, a method for forming fully recessed (planar) isolation regions (22,24) on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate with mesas formed therein, forming low viscosity sidewall spacers of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein.
39
Patent
Selective epitaxy BiCMOS process
P. J. Howell
- 19 Jan 1989
TL;DR: In this article, a process for fabricating both bipolar and complementary field effect transistors in an integrated circuit is described, which includes the steps of removing all the epitaxial layer 15 and all of the buried layer 12 from regions of the substrate where NMOS devices are to be formed.
33
Patent
Stem of a joint endoprosthesis
Kallabis Manfred Dr,Gombert Guido Dr +1 more
- 14 Jul 1988
TL;DR: In the proximal region of the stem (10) there is a cutout (14) into which a screw spindle (30) is screwed after surgical insertion of a stem into the thigh bone.
1
Patent
Process for forming isolation regions in a semiconductor substrate.
Steven Shao-Lun Lee
- 18 Nov 1988
TL;DR: In this article, an isolation structure formation process such that the trenches (12, 14, 17) formed in a semiconductor substrate between adjacent regions of epitaxial silicon and the substrate is to form recesses is described.
References
Patent
Dynamic memory cell with two complementary bipolar transistors
Badih El-Kareh
- 25 Sep 1980
TL;DR: An improved dynamically operated memory cell consisting of two complementary bipolar transistors was described for the construction of a highly integrated semiconductor memory whose memory cells (18) lie at the intersection of word and bit lines as mentioned in this paper.
1
Patent
Integrierte injektions-halbleiterschaltung und verfahren zu ihrer herstellung
James Glenn Aiken,Benjamin J. Sloan +1 more
- 12 Apr 1977
1