Verifying parallel dataflow transformations with model checking and its application to FPGAs

TL;DR: Accelerated SAT solver on FPGA accelerates Boolean Constraint Propagation (BCP) through fine-grained parallelism and eliminates clause look-up operations.

TL;DR: In this paper , a throughput-buffering trade-off exploration that uses K-periodic scheduling to direct a design-space exploration is proposed, which provides optimal solutions while significantly reducing the search space compared to existing methodologies.

TL;DR: Researchers propose a software interpretation method for High Level Synthesis, using a formal power consumption model to accurately predict power consumption and simplify re-use of power optimizations across distinct application-specific circuit designs.

TL;DR: At its most elemental level, OpenMP is a set of compiler directives and callable runtime library routines that extend Fortran (and separately, C and C++ to express shared memory parallelism) and leaves the base language unspecified.

TL;DR: This report introduces TLA and describes how it is used to specifying and verify concurrent algorithms and the use of TLA to specify and reason about open systems will be described elsewhere.

TL;DR: It is shown that on real and synthetic applications, the “work” and “critical-path length” of a Cilk computation can be used to model performance accurately, and it is proved that for the class of “fully strict” (well-structured) programs, the Cilk scheduler achieves space, time, and communication bounds all within a constant factor of optimal.

TL;DR: This self-contained paper develops the theory necessary to statically schedule SDF programs on single or multiple processors, and a class of static (compile time) scheduling algorithms is proven valid, and specific algorithms are given for scheduling SDF systems onto single ormultiple processors.