Patent
Variable shift register
Gary Blake Cole,Michael J. Gingell +1 more
- 11 Dec 1990
11
TL;DR: In this paper, a variable length shift register is formed of a plurality of flip-flops arranged to form separate shift registers of different lengths, interconnected by multiplexers which connect either the input or output of each shift register to the input of an adjacent shift register.
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Abstract: A variable length shift register is formed of a plurality of flip-flops arranged to form separate shift registers of different lengths. The shift registers are interconnected by multiplexers which connect either the input or the output of each shift register to the input of an adjacent shift register. Control signals are provided to the multiplexers to controllably select the length of the variable shift register by selectively inserting shift registers into the variable shift register and bypassing others.
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Citations
Patent
Integrated circuit having a shift stage count changing function
Minoru Hirai
- 14 Jun 1993
TL;DR: In this article, the serial data consisting of a number of bits exceeding the setup stage count is input, and the serial-parallel converter outputs data as overflow serial data in order starting at the first input bit of serial data.
19
Patent
Successive-approximation register
David Robert Brooks
- 29 Nov 1989
TL;DR: In this article, a successive approximation register (SAR) is proposed, which adopts a "One-bits to right" test implemented by a Manchester Carry Chain in the opposite direction to the shift direction.
12
Patent
Digital-to-analog converter with a flexible data interface
Robert C. Ledzius,James S. Irwin,Dhirajlal N. Manvar +2 more
- 30 Mar 1992
TL;DR: In this article, a flexible data interface (21, 22) for a digital-to-analog converter (25, 26) includes a mute circuit (46, 70, 71 ) to mute and de-mute input data in 6 dB steps over a time period such as one-quarter of a second.
12
Patent
N-bit parallel input to variable-bit parallel output shift register
Richard William Peters
- 16 Dec 1991
TL;DR: In this article, a bit stuffing technique is used to start a payload envelope pattern at a selected location in a synchronous transport signal frame by monitoring a frame starting signal and providing a pattern starting signal at a specified point after the occurrence of the frame starting signals.
11
Patent
One-pin shift register interface
Eric N. Mann
- 13 Feb 1997
TL;DR: In this article, a three-level receiver, a latch and an output driver are combined to form a one-pin bidirectional interface used with a shift register, which allows the programming of an erasable programmable read only memory (EPROM) in a clock chip while utilizing the fewest number of pins.
9
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Patent
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Patent
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Patent
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Hartmeier Werner Niklaus
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TL;DR: In this article, a transition enhancing circuit includes a tapped delay line which provides successively delayed replicas of the signal to be processed, and a multiplexer, responsive to a signal transition, sequentially couples delayed signal from the center tap and taps more distant from the input of the delay line to an output terminal.
17
Patent
Digital data storage with equal input and output data rate, but variable memory shift rate
G Toyen
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TL;DR: In this article, the storage capacity or length of a memory consisting of shift registers which may only be available in certain discrete bit lengths is controlled or programmed by shifting data from each stage of an input serial to parallel shift register into different ones of the memory shift registers and then transferring the data from the output stages of memory registers into an output parallel to serial shift register.
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