What is the first step in the SAT debugging process?

the circuit is transformed into a SAT instance, the primary inputs are constrained to the values given by a failure trace and the outputs are restricted to the correct output value.

How many times does the standard debugging approach take?

For small fault candidates (k ≤ 2) and circuits with less than 1000 abnormal predicates, the standard debugging approach often needs less than one second.

What is the SAT solver's ability to change the value of a gate?

Additional logic is used to change values of internal signals: the Boolean function g of a gate is replaced by ag → g, i.e., if ag = 0, the gate works as usual; if ag = 1, the output value of the gate is unrestricted.

What is the advantage of Reiter’s approach?

Whereas Reiter’s approach calls the proof engine for each assumption in the conflicting set, their approach has the decisive advantage of only requiring as many calls to the SAT solver as there are components in the fault candidate (plus one call for every further fault candidate).

What are some of the methods that are used to aid debugging?

Some of them rely on simulation [19] or structural properties of the debugging problem [9], others use strong reasoning engines [5].

What is the purpose of the SAT solver?

A SAT solver is applied to extract an unsatisfiable core, i.e., a part of the SAT problem that is already unsatisfiable [4, 21, 14].

What are the constraints to limit the abnormal predicates?

Knowing that the cores are non-overlapping and that one abnormal predicate per core must be 1, only |core1| · |core2|/2 of these possibilities have to be considered.

What is the process for determining the unsat cores?

the process depends on the order in which the unsat cores are found, e.g., this determines how many abnormal predicates have to be considered during the standard SAT based debugging process.

What is the solution space of the method?

The solution space of their method is identical to the standard approach for SAT-based debugging: all fault candidates of minimal cardinality are returned.

Open AccessProceedings Article10.1145/1366110.1366131

Using unsatisfiable cores to debug multiple design errors

Andre Suelflow, +3 more

- 04 May 2008

- pp 77-82

TL;DR: Unsatisfiable cores contained in a SAT instance for debugging are used to determine all suspects, and to speed-up the debugging process for debugging multiple faults.

Abstract: Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported quite well using simulation or formal verification. But locating the fault site is typically a time consuming manual task. Techniques to automate debugging and diagnosis have been proposed. Approaches based on Boolean Satisfiability (SAT) have been demonstrated to be very effective. In this work debugging on the gate level is considered. Unsatisfiable cores contained in a SAT instance for debugging are used (1) to determine all suspects, and (2) to speed-up the debugging process. In comparison to standard SAT-based debugging, the experimental results show a significant speed-up for debugging multiple faults.

AI Agents for this Paper

Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps

Most frequently asked questions

1. What contributions have the authors mentioned in the paper "Using unsatisfiable cores to debug multiple design errors" ?

In this work debugging on the gate level is considered.

2. What are the future works mentioned in the paper "Using unsatisfiable cores to debug multiple design errors" ?

It remains future work to consider the sequential case more thoroughly, for instance by considering the distance in time between a fault candidate and the observation of a fault [ 7 ].. Moreover, exploiting incremental SAT within their framework more efficiently by keeping detailed information about learned clauses [ 14 ] may further improve the performance.

3. How many cores were extracted using standard debugging?

For instance, for misex3 the 2 cores were obtained by the SAT solver using propagation only, in less than 1% of the run time of the standard debugging method.

4. How long did the standard debugging approach take to find the fault sites?

For instance, for x3 all fault sites were extracted within one minute, whereas the standard debugging approach needs more than eight minutes.

Citations

Book Chapter•10.1007/978-3-642-02658-4_11

Explaining Counterexamples Using Causality

Ilan Beer, +4 more

- 23 Jun 2009

TL;DR: This paper formally defines a set of causes for the failure of the specification on the given counterexample trace, marked as red dots and presented to the user as a visual explanation of the failure, and provides a polynomial-time algorithm that approximates it.

...read moreread less

144

•Journal Article•10.1109/TCAD.2010.2061270

Automated Design Debugging With Maximum Satisfiability

Yibin Chen, +3 more

- 01 Nov 2010

- IEEE Transactions on Computer-Aided Desi...

TL;DR: This paper presents a novel formulation of the debugging problem using MaxSAT to improve the performance and applicability of automated debuggers, and introduces two performance improvements to further reduce the time required to find all error sources within the design by an order of magnitude.

...read moreread less

101

•Proceedings Article•10.5555/2157654.2157667

Post-silicon fault localisation using maximum satisfiability and backbones

Charlie Shucheng Zhu, +2 more

- 30 Oct 2011

TL;DR: It is proposed to slide a smaller window along the temporal axis, constraining it with the information recorded in the trace buffer for the respective execution cycles, to address the scalability issues resulting from large window sizes.

...read moreread less

•Book

Advanced Techniques in Logic Synthesis, Optimizations and Applications

Victor N. Kravets, +7 more

- 03 Dec 2010

TL;DR: This book covers recent advances in the field of logic synthesis and design, including Boolean Matching, Logic Decomposition, Boolean satisfiability, Advanced Synthesis Techniques and Applications of Logic Design.

...read moreread less

•Proceedings Article•10.1109/RSP.2009.21

WoLFram- A Word Level Framework for Formal Verification

André Sülflow, +4 more

- 23 Jun 2009

TL;DR: The word level framework WoL Fram is presented that enables the development of applications for formal verification of systems independent of the underlying proof technique, and makes WoLFram a stable backbone for the development and quick evaluation of emerging verification techniques.

...read moreread less

...

Expand

References

Proceedings Article•10.1145/378239.379017

Chaff: engineering an efficient SAT solver

Matthew W. Moskewicz, +4 more

- 22 Jun 2001

TL;DR: The development of a new complete solver, Chaff, is described which achieves significant performance gains through careful engineering of all aspects of the search-especially a particularly efficient implementation of Boolean constraint propagation (BCP) and a novel low overhead decision strategy.

...read moreread less

3.5K

Book Chapter•10.1007/978-3-540-24605-3_37

An Extensible SAT-solver

Niklas Een, +1 more

- 05 May 2003

TL;DR: This article presents a small, complete, and efficient SAT-solver in the style of conflict-driven learning, as exemplified by Chaff, and includes among other things a mechanism for adding arbitrary boolean constraints.

...read moreread less

3.4K

Journal Article•10.1016/0004-3702(87)90062-2

A theory of diagnosis from first principles

Raymond Reiter

- 01 Oct 1987

- Artificial Intelligence

TL;DR: The theory accommodates diagnostic reasoning in a wide variety of practical settings, including digital and analogue circuits, medicine, and database updates, and reveals close connections between diagnostic reasoning and nonmonotonic reasoning.

...read moreread less

3.2K

•Journal Article•10.1109/12.769433

GRASP: a search algorithm for propositional satisfiability

Joao Marques-Silva, +1 more

- 01 May 1999

- IEEE Transactions on Computers

TL;DR: Experimental results obtained from a large number of benchmarks indicate that application of the proposed conflict analysis techniques to SAT algorithms can be extremely effective for aLarge number of representative classes of SAT instances.

...read moreread less

1.6K

Journal Article•10.1007/S10817-007-9084-Z

Algorithms for Computing Minimal Unsatisfiable Subsets of Constraints

Mark H. Liffiton, +1 more

- 01 Jan 2008

- Journal of Automated Reasoning

TL;DR: This paper describes a relationship between satisfiable and unsatisfiable subsets of constraints that is subsequently used as the foundation for MUS extraction algorithms, implemented for Boolean satisfiability constraints.

...read moreread less

408

...

Expand

Using unsatisfiable cores to debug multiple design errors

Chat with Paper

AI Agents for this Paper

Most frequently asked questions

1. What contributions have the authors mentioned in the paper "Using unsatisfiable cores to debug multiple design errors" ?

2. What are the future works mentioned in the paper "Using unsatisfiable cores to debug multiple design errors" ?

3. How many cores were extracted using standard debugging?

4. How long did the standard debugging approach take to find the fault sites?

5. What is the first step in the SAT debugging process?

6. How many times does the standard debugging approach take?

7. What is the SAT solver's ability to change the value of a gate?

8. What is the advantage of Reiter’s approach?

9. What are some of the methods that are used to aid debugging?

10. how to exploit incremental SAT within their framework?

11. What is the purpose of the SAT solver?

12. What are the constraints to limit the abnormal predicates?

13. What is the process for determining the unsat cores?

14. What is the solution space of the method?

Figures

Citations

Explaining Counterexamples Using Causality

Automated Design Debugging With Maximum Satisfiability

Post-silicon fault localisation using maximum satisfiability and backbones

Advanced Techniques in Logic Synthesis, Optimizations and Applications

WoLFram- A Word Level Framework for Formal Verification

References

Chaff: engineering an efficient SAT solver

An Extensible SAT-solver

A theory of diagnosis from first principles

GRASP: a search algorithm for propositional satisfiability

Algorithms for Computing Minimal Unsatisfiable Subsets of Constraints

Related Papers (5)

Fault diagnosis and logic debugging using Boolean satisfiability

An Extensible SAT-solver

Improved Design Debugging Using Maximum Satisfiability

Automated Design Debugging With Maximum Satisfiability

Design error diagnosis and correction via test vector simulation