Patent
Two{3 s complement parallel array multiplier
Baugh Charles Richmond,Wooley Bruce Allen +1 more
- 01 Apr 1974
21
TL;DR: In this paper, an array of 3-bit adders is constructed from a combination of threshold logic modules, and the resulting simplifications permit circuit realization in the form of an array.
read more
Abstract: Apparatus and methods for performing the parallel m-bit by n-bit multiplication of two binary 2's complement numbers by converting the multiplication process to an equivalent parallel array addition in which the operands are positive partial products including (1) terms formed by ANDing a multiplier bit (or its complement), and (2) a multiplicand bit (or its complement) and five additional partial product terms. The resulting simplifications permit circuit realization in the form of an array of 3-bit adders each formed from a combination of threshold logic modules.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Electrooptical matrix multiplication using the twos complement arithmetic for improved accuracy
TL;DR: The improved electrooptic signal processing relies upon matrix-matrix multiplication using twos complement arithmetic that provides for a convenient means for handling bipolar numbers, avoids the need for matrix partitioning when the matrices are real and offers a means to improve accuracy over conventional optical analog techniques.
76
Patent
Fast regular multiplier architecture
Ingrid Verbauwhede
- 22 Oct 1998
TL;DR: In this article, a Hekstra-type multiplier is modified by replacing many of the full adders circuits with compressor circuits in a manner that preserves the balance of the signal delays between the various propagation paths through the summing stages.
71
Patent
Reconfigurable arithmetic datapath
Curtis Abbott
- 17 Oct 1997
TL;DR: In this article, a method and apparatus that combines the same basic hardware elements in several ways to perform a plurality of arithmetic operations over different numbers of operands of different lengths is presented.
26
Patent
Two's complement multiplication with a sign magnitude multiplier
Stamatis Vassiliadis,Eric M. Schwarz,Baik Moon Sung +2 more
- 24 Nov 1989
TL;DR: A multi-bit overlapped scanning multiplication system using overlapped partial products in a matrix, accepts and multiplies either sign-magnitude operands or signed binary operands without correction, conversion, or complementation of operators or results as discussed by the authors.
24
Patent
Digital multiplier architecture with triple array summation of partial products
James Yuan Wei,Hedayati Khosrow +1 more
- 31 Aug 1987
TL;DR: In this article, a modified Booth algorithm was proposed to minimize the number of partial products generated by the two adder arrays in order to optimize the speed of the circuit, where the partial products are divided between the two arrays in a manner which optimizes the speed.
24
References
A Two's Complement Parallel Array Multiplication Algorithm
C.R. Baugh,Bruce A. Wooley +1 more
TL;DR: An algorithm for high-speed, two's complement, m-bit by n-bit parallel array multiplication is described, which is converted to an equivalent parallel array addition problem in which each partial product bit is the AND of a multiplier bit and a multiplicand bit.
717
Related Papers (5)
Lin Yang,Chun-Ling Liu +1 more
- 12 Nov 1992
William L. Borgerding,Vithal R. Patel +1 more
- 10 Mar 1981