Patent
Transparent system interrupt
James P. Kardach,Gregory S. Mathews,Cau Nguyen,Sung S. Cho,Kameswaran Sivamani,David S. Vannier,Shing Wong,Edward Zager +7 more
- 06 Nov 1991
86
TL;DR: In this paper, a transparent system interrupt is invoked by the assertion of an electrical signal at an external pin of a microprocessor CPU chip, and the CPU begins program execution in a dedicated RAM area that is inaccessible both to the operating system and all application programs.
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Abstract: A transparent system interrupt is invoked by the assertion of an electrical signal at an external pin of a microprocessor CPU chip. Upon assertion of this interrupt, the CPU begins program execution in a dedicated RAM area that is inaccessible both to the operating system and all application programs. A set of instructions, which may be unique to the system in which the CPU chip is installed, services the interrupt. Typically, the state of the CPU and associated components in the system immediately prior to assertion of the interrupt will be saved into the dedicated RAM area by the interrupt service routine. Recovery from the interrupt is accomplished upon recognition of an external event that invokes a RESUME instruction causing the CPU and associated components to be restored to exactly the same state that existed prior to the interrupt and in a manner entirely transparent to any program executing at the time of the interrupt.
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Citations
Patent
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228
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- 12 Mar 1996
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173
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170
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- 21 Sep 1998
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140
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James G. Letwin
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Patent
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Mark Poret,Jeanne McKinley +1 more
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TL;DR: In this paper, a circuit for in-circuit emulation (ICE) of a microprocessor system is described, which allows a user to perform in-Circuit emulation ("ICE") for the purpose of debugging the microprocessor systems.
182
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Apparatus and method for suspending and resuming software applications on a computer
Ronald Xavier Arroyo,Michael Norman Day,Jimmie Darius Edrington,James T. Hanna,Gary T. Hunt,Steven T Pancoast +5 more
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TL;DR: In this article, a method and apparatus for powering down a computer system while saving the state of the system at power down is described, where the contents of all active registers as well as the states of all I/O devices in the system are stored in a save area of system memory.
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