Journal Article10.1145/254180.254184
Trace-driven memory simulation: a survey
Richard Uhlig,Trevor Mudge +1 more
332
TL;DR: A survey and analysis of trace-driven memory simulation tools can be found in this article, where the authors discuss the strengths and weaknesses of different approaches and show that no single method is best when all criteria, including accuracy, speed, memory, flexibility, portability, expense, and ease of use are considered.
read more
Abstract: As the gap between processor and memory speeds continues to widen, methods for evaluating memory system designs before they are implemented in hardware are becoming increasingly important. One such method, trace-driven memory simulation, has been the subject of intense interest among researchers and has, as a result, enjoyed rapid development and substantial improvements during the past decade. This article surveys and analyzes these developments by establishing criteria for evaluating trace-driven methods, and then applies these criteria to describe, categorize, and compare over 50 trace-driven simulation tools. We discuss the strengths and weaknesses of different approaches and show that no single method is best when all criteria, including accuracy, speed, memory, flexibility, portability, expense, and ease of use are considered. In a concluding section, we examine fundamental limitations to trace-driven simulation, and survey some recent developments in memory simulation that may overcome these bottlenecks.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
A methodology for architecture exploration of heterogeneous signal processing systems
Paul Lieverse,P. van der Wolf,Ed F. Deprettere,Kornelis A. Vissers +3 more
- 20 Oct 1999
TL;DR: The methodology provides a means to quickly build models of architectures at an abstract level, to easily map applications, modeled as Kahn Process Networks, onto these architecture models, and to analyze the performance of the resulting system by simulation.
236
PEBIL: Efficient static binary instrumentation for Linux
Michael A. Laurenzano,Mustafa M. Tikir,Laura Carrington,Allan Snavely +3 more
- 28 Mar 2010
TL;DR: A static binary instrumentation toolkit forLinux on the x86/x86_64 platforms, PEBIL (PMaC's Efficient Binary Instrumentation Toolkit for Linux) is presented, designed with the primary goal of producing efficient-running instrumented code.
Analytical cache models with applications to cache partitioning
G. Edward Suh,Srinivas Devadas,Larry Rudolph +2 more
- 17 Jun 2001
TL;DR: In this paper, an analytical cache model for time-shared systems is presented, which estimates the overall cache miss-rate of a multiprocessing system with any cache size and time quanta.
Quantifying Locality In The Memory Access Patterns of HPC Applications
Jonathan Weinberg,Michael O. McCracken,Erich Strohmaier,Allan Snavely +3 more
- 12 Nov 2005
TL;DR: In this paper, the authors propose a methodology for producing architecture-neutral characterizations of the spatial and temporal locality exhibited by the memory access patterns of applications and demonstrate that the results track intuitive notions of locality on several synthetic and application benchmarks.
A Survey of Computer Architecture Simulation Techniques and Tools
Ayaz Akram,Lina Sawalha +1 more
TL;DR: The fundamentals of different computer architecture simulation techniques are reviewed and a detailed comparison of these simulators based on other features such as flexibility and micro-architectural details is performed.
References
•Book
Computer Architecture: A Quantitative Approach
John L. Hennessy,David A. Patterson +1 more
- 01 Dec 1989
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
12.6K
A universal algorithm for sequential data compression
Jacob Ziv,A. Lempel +1 more
TL;DR: The compression ratio achieved by the proposed universal code uniformly approaches the lower bounds on the compression ratios attainable by block-to-variable codes and variable- to-block codes designed to match a completely specified source.
Cache Memories
TL;DR: Specific aspects of cache memories investigated include: the cache fetch algorithm (demand versus prefetch), the placement and replacement algorithms, line size, store-through versus copy-back updating of main memory, cold-start versus warm-start miss ratios, mulhcache consistency, the effect of input /output through the cache, the behavior of split data/instruction caches, and cache size.
1.6K
•Book
Distributed Operating Systems
Andrew S. Tanenbaum,Robbert van Renesse +1 more
- 30 Jan 2009
TL;DR: What constitutes a distributed operating system and how it is distinguished from a computer network are discussed, and several examples of current research projects are examined in some detail.
1.4K
Evaluation techniques for storage hierarchies
TL;DR: A new and efficient method of determining, in one pass of an address trace, performance measures for a large class of demand-paged, multilevel storage systems utilizing a variety of mapping schemes and replacement algorithms.
1.4K