Toward Precise PLRU Cache Analysis.
Daniel Grund,Jan Reineke +1 more
- 01 Jan 2010
- Vol. 15, pp 23-35
TL;DR: A must-analysis of the tree-based PLRU cache replacement policy (pseudo least-recently used) is defined, which is more precise than prior ones by excluding spurious logarithmic-time eviction.
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Abstract: Schedulability analysis for hard real-time systems requires bounds on the execution times of its tasks. To obtain useful bounds in the presence of caches, cache analysis is mandatory. The subject-matter of this article is the static analysis of the tree-based PLRU cache replacement policy (pseudo least-recently used), for which the precision of analyses lags behind those of other policies. We introduce the term subtree distance, which is important for the update behavior of PLRU and closely linked to the peculiarity of PLRU that allows cache contents to be evicted in “logarithmic time”. Based on an abstraction of subtree distance, we define a must-analysis that is more precise than prior ones by excluding spurious logarithmic-time eviction.
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Citations
A Survey on Cache Management Mechanisms for Real-Time Embedded Systems
TL;DR: This article presents a survey of cache management techniques for real-time embedded systems, from the first studies of the field in 1990 up to the latest research published in 2014, and provides a detailed comparison in terms of similarities and differences.
A Survey on Static Cache Analysis for Real-Time Systems
TL;DR: This article provides a survey on static cache analysis for real-time systems, presenting the challenges and static analysis techniques for independent programs with respect to different cache features, followed by a survey of existing tools based on static techniques for cache analysis.
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A Unified WCET analysis framework for multicore platforms
Sudipta Chattopadhyay,Lee Kee Chong,Abhik Roychoudhury,Timon Kelter,Peter Marwedel,Heiko Falk +5 more
TL;DR: This work differs by modeling the interaction of shared cache and shared bus with other basic micro-architectural components (e.g. pipeline and branch predictor) by assuming a timing anomaly free multi-core architecture for computing the WCET.
Static probabilistic timing analysis for real-time systems using random replacement caches
TL;DR: It is proved that one of the previously published formulae for the probability of a cache hit is optimal with respect to the limited information (reuse distance and cache associativity) that it uses, and an alternative formulation is derived that makes use of additional information in the form of the number of distinct memory blocks accessed (the stack distance).
Randomized Caches Considered Harmful in Hard Real-Time Systems
TL;DR: It is concluded that with prevailing static and measurement-based analysis techniques caches with deterministic placement and least-recently-used replacement are preferable over randomized ones.
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