Timing optimization by bit-level arithmetic transformations
L. Rijnders,Z. Sahraoui,P. Six,H. De Man +3 more
- 01 Dec 1995
- pp 48-53
TL;DR: The method forms a link between data path optimizations at the word level and logic synthesis techniques at the bit level, and is especially suited to optimize large adder structures inside these data paths.
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Abstract: This paper describes a method to optimize the performance of data paths. It is based on bit-level arithmetic transmutations, and is especially suited to optimize large adder structures inside these data paths. The multi-operand adders are identified at the bit level and the addition parts are merged even across operator boundaries. Area and delay optimizations use CSD coding and timing-driven transformations, including bit-slice adder trees and logarithmic addition. The method forms a link between data path optimizations at the word level and logic synthesis techniques at the bit level. Experiments show that starting from a very simple description of an N/spl times/N multiplier an O(log N) delay is obtained with very low run times.
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Citations
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Patrick Schaumont,B. Vanthournout,Ivo Bolsens,H. De Man +3 more
- 13 Sep 1995
TL;DR: In this article, a methodology is presented to synthesize high throughput DSP functions into accelerator processors containing a datapath of highly pipelined, bit-parallel hardware units.
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Kei-Yong Khoo,Zhan Yu,Alan N. Willson +2 more
- 07 Nov 1999
TL;DR: By relaxing the carry-save representation to allow for more than two signals per bit position, this work gains flexibility in the bit-level implementation of CSA arrays that can be exploited to achieve a more efficient design.
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Design of Low-Power Reduction-Trees in Parallel Multipliers
Saeeid Tahmasbi Oskuii
- 01 Jan 2008
TL;DR: Optimization methods, utilizing the arithmetic equivalencies in the partial product reduction trees, are proposed in order to reduce the dynamic power, static power, or total power which is a combination of dynamic and static power.
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Synthesis of pipelined DSP accelerators with dynamic scheduling
Patrick Schaumont,B. Vanthournout,Ivo Bolsens,H. De Man +3 more
- 01 Jan 1997
TL;DR: In this article, a methodology is presented to synthesize high throughput DSP functions into accelerator processors containing a datapath of highly pipelined, bit-parallel hardware units.
7
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