Tiling Nested Loops into Maximal Rectangular Blocks

TL;DR: This work derives the optimal mapping and scheduling of tiles to physical processors under some reasonable assumptions, under the context of limited computational resources, and assuming communication-computation overlap.

TL;DR: An efficient algorithm to implement loop partitioning is introduced and an efficient heuristic to determine the optimal tile shape is designed, showing its usefulness using both examples of Agarwal et al. and a large collection of randomly generated data.

TL;DR: A suite of compiler techniques for generating efficient SPMD programs to execute rectangularly tiled iteration spaces on distributed memory machines and two memory optimisations are given to reduce the amount of memory usage for skewed iteration spaces and expanded arrays, respectively.

TL;DR: This work derives the optimal mapping and scheduling of tiles to physical processors under some reasonable assumptions, under the context of limited computational resources and assuming communication‐computation overlap.

TL;DR: This paper presents a meta-modelling architecture for supercompilers that automates the very labor-intensive and therefore time-heavy and expensive process of learning and optimization of supercomputing systems.

TL;DR: The loop transformation theory is applied to the problem of maximizing the degree of coarse- or fine-grain parallelism in a loop nest and it is shown that the maximum degree of parallelism can be achieved by transforming the loops into a nest of coarsest fullypermutable loop nests and wavefronting the fully permutable nests.

TL;DR: Methods are developed for the parallel execution of different iterations of a DO loop and practical application to the design of compilers for such computers is discussed.

TL;DR: A class of partitionings is presented that encompasses previous techniques and provides enough flexibility to adapt code to multiprocessors with two levels of parallelism and two level of memory.