Thyristor provided with buffer layer structure

TL;DR: In this paper, a PNPN four-layer three-end structure with buffer layer N 0 area is proposed to solve the problem of big voltage drop, slow switch speed and the like existing in a current thyristor when applied to a high-frequency high-power converter power supply and a pulsed power supply.

Abstract: The utility model relates to a thyristor provided with a buffer layer structure, which belongs to the technical field of power semiconductor devices, and mainly solves such problems as big voltage drop, slow switch speed and the like existing in a current thyristor when the thyristor is applied to a high-frequency high-power converter power supply and a pulsed power supply. The thyristor is mainly characterized by comprising a shell and a semiconductor chip which is packaged in the shell and of a PNPN four-layer three-end structure; and a buffer layer N0 area is added between a P1 area and a N1 area in the semiconductor chip, the surface concentration of the N1 area is 10-200 times higher than that of the N0 area, and 50-500 times lower than that of the P1 area. The thyristor has the characteristics that on-state voltage drop can be dropped obviously when the thyristor is applied to the high-power converter power supply and the pulsed power supply, thereby bettering an on-state ability, improving the work reliability, optimizing an internal structure, reducing big injection stored charge, and improving recovery softness. The thyristor provided by the utility model is mainly applied to high-power pulsed power supply devices.