Patent
Three-dimensional multi-chip pad array carrier
Paul T. Lin
- 02 Mar 1992
486
TL;DR: In this paper, a stackable three-dimensional multi-chip module (MCM) is provided whereby each level of chip carrier is interconnected to another level through reflowing of solder balls pre-bumped onto each carrier.
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Abstract: A stackable three-dimensional multi-chip module (MCM) is provided whereby each level of chip carrier is interconnected to another level of chip carrier through reflowing of solder balls pre-bumped onto each carrier. Each level of chip carrier, except for the top carrier, has solder balls on both top and bottom surfaces of the substrate. Optional lids can be used to seal each device, and the lid height would serve as a natural positive stand-off between each level of carriers, giving rise to hour glass shaped solder joints which maximizes the fatigue life of the joints. Heat sinks to further enhance heat dissipation of the MCM can be easily accommodated in this stacking approach. Furthermore, each substrate is capable of carrying multiple chips, so the module incorporates planar chip density growth concurrently with the three-dimensional growth giving rise to an ultradense MCM.
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Citations
Patent
Semiconductor device, and manufacturing method thereof
Kengo Akimoto,Tatsuya Honda,Norihito Sone +2 more
- 01 Aug 2008
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
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A review of 3-D packaging technology
TL;DR: In this paper, the state-of-the-art in 3D packaging technology for very large scale integration (VLSI) is reviewed, where a number of bare dice and multichip module (MCM) stacking technologies are emerging to meet the ever increasing demands for low power consumption, low weight and compact portable systems.
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- 20 Dec 2006
TL;DR: A microelectronic package as discussed by the authors includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the micro-electronic element, whereby at least one of the posts is disposed in the outer region of a substrate.
383
Patent
Stacked microelectronic assembly and method therefor
Young Kim,Belgacem Haba,Vernon Solberg +2 more
- 02 Feb 2001
TL;DR: In this paper, a method of making a stacked microelectronic assembly includes providing a flexible substrate having a plurality of attachment sites, test contacts and conductive terminals, and including a wiring layer with leads extending to the attachment sites.
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Stackable ball grid array package
David J. Corisis,Jerry M. Brooks,Walter L. Moden +2 more
- 30 Jul 2001
TL;DR: In this paper, a stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA.
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Patent
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- 18 Jul 1990
TL;DR: In this article, the melting point of the second solder ball portion is relatively higher than that of the first solder portion, and a method of testing the solderability of the above structures is presented.
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Patent
Process for controlling solder joint geometry when surface mounting a leadless integrated circuit package on a substrate
Francis Lovasco,Michael Ackman Oien +1 more
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TL;DR: In this paper, a solder joint assembly technique applies controlled volumes of solder to pads of both package and substrate, and the two units are positioned adjacent each other with the pads and solder deposits mechanically maintained in registration with each other.
198
Patent
Slip controller for automobile
Yasuhiro Harada,Nishimura Shigemochi,Kazutoshi Nobumoto,Toru Onaka +3 more
- 28 Jul 1986
TL;DR: In this article, an altering device which alters a speed of response to the direction of increasing the torque given to the driving wheels so as to make it smaller as compared with the time of being hard to slip when a road surface is liable to slip.
66
3-D interconnection for ultra-dense multichip modules
C. Val,T. Lemoine +1 more
- 20 May 1990
TL;DR: In this paper, a three-dimensional interconnection technology is described that allows a reduction of the occupied area by a factor of 7 or 8 as against 2-D interconnection, which consists of interconnecting the bare chips not in the XY plane, but along the Z-axis.
57
Patent
Semiconductor packaging and method
Paul T. Lin
- 15 May 1986
TL;DR: A mounting means for a semiconductor integrated circuit is defined in this paper, which consists of a material having a mounting surface as one major surface of the semiconductor material and means for electrically connecting the integrated circuit to the material.
52
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