Patent
Three-dimensional memory device containing vertically isolated charge storage regions and method of making thereof
Rahul Sharangpani,Raghuveer S. Makala,Senaka Kanakamedala,Fei Zhou,Somesh Peri,Masanori Tsutsumi,Keerti Shukla,Yusuke Ikawa,Kiyohiko Sakakibara,Eisuke Takii +9 more
- 29 Aug 2016
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TL;DR: A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers provided over a substrate as discussed by the authors, where the annular etch stop material portions are provided at each level of the sacrificial materials layers around the memory opening.
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Abstract: A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers provided over a substrate Annular etch stop material portions are provided at each level of the sacrificial material layers around the memory opening The annular etch stop material portions can be formed by conversion of surface portions of the sacrificial material layers into dielectric material portion, or by recessing the sacrificial material layers around the memory opening and filling indentations around the memory opening After formation of a memory stack structure, the sacrificial material layers are removed from the backside The annular etch stop material portions are at least partially converted to form charge trapping material portions Vertical isolation of the charge trapping material portions among one another around the memory stack structure minimizes leakage between the charge trapping material portions located at different word line levels
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Citations
Patent
Memory device and method for fabricating the same
Sheng-Chih Lai,Wei-Chen Chen +1 more
- 20 Jul 2015
TL;DR: In this paper, a memory device comprises a first conductive stripe, a memory layer, a first pillar, a dielectric layer, and a first plug, where the first pillar is electrically insulated from the first memory layer.
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Kai James,Murshed Chowdhury,Jin Liu,Alsmeier Johann +3 more
- 21 Mar 2018
TL;DR: In this article, a three-dimensional memory device including self-aligned drain select level electrodes is provided, where the memory stack structures extend through an alternating stack of insulating layers and spacer material layers.
15
Patent
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Akira Goda,Hu Yushi +1 more
- 01 Feb 2017
TL;DR: In this paper, the authors describe a NAND memory array which has a vertical stack of alternating insulative levels and wordline levels, and charge-trapping material along vertically adjacent word line levels is spaced by intervening regions through which charge migration is impeded.
12
Patent
Memory arrays, and methods of forming memory arrays
David Daycock,Hill Richard J,Christopher J. Larsen,Woohee Kim,Dorhout Justin B,Brett D. Lowe,Hopkins John D,Tao Qian,Casey Barbara L +8 more
- 22 Mar 2018
TL;DR: In this paper, a memory array which has a vertical stack of alternating insulative levels and wordline levels has been described, where charge-trapping material is along the control gate regions of the wordline level and not along the insulative level.
11
Patent
Methods of forming an array of elevationally-extending strings of memory cells
Howder Collin,Meyer Ryan,Chet E. Carter +2 more
- 19 Mar 2019
TL;DR: In this paper, a method of forming an array of elevationally-extending strings of memory cells comprises forming conductively-doped semiconductor material directly above and electrically coupled to metal material.
7
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Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory
Jae-Hoon Jang,Han-soo Kim,Wonseok Cho,Hoosung Cho,Jinho Kim,Sun Il Shim,Younggoan Jang,Jae-Hun Jeong,Byoungkeun Son,Dongwoo Kim,Kihyun,Jae-Joo Shim,Jin Soo Lim,Kyoung-hoon Kim,Su Youn Yi,Ju-Young Lim,De-will Chung,Hui-chang Moon,Sung-Min Hwang,Jong-Wook Lee,Yong-Hoon Son,U-In Chung,Won-Seong Lee +22 more
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TL;DR: Damascened metal gate SONOS type cell in the vertical NAND flash string is realized by a unique dasiagate replacementpsila process and conventional bulk erase operation of the cell is successfully demonstrated.
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Patent
Non-volatile semiconductor storage device and method of manufacturing the same
Yoshiaki Fukuzumi,Ryota Katsumata,Masaru Kidoh,Masaru Kito,Hiroyasu Tanaka,Yosuke Komori,Megumi Ishiduki,Hideaki Aochi +7 more
- 09 Sep 2009
TL;DR: In this paper, a nonvolatile semiconductor storage device has a plurality of memory strings to each of which an electrically rewritable memory cells are connected in series, each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate.
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