Patent
Three dimensional memory device containing multilayer wordline barrier films and method of making thereof
Rahul Sharangpani,Fumitaka Amano,Raghuveer S. Makala,Fei Zhou,Keerti Shukla +4 more
- 10 Apr 2017
16
TL;DR: Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers, and backside recesses are formed by removal of the sacrificial materials layers selective to the insulating layer and the memory stack structures.
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Abstract: Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. A barrier layer stack including a crystalline electrically conductive barrier layer and an amorphous barrier layer is formed in the backside recesses prior to formation of a metal fill material layer.
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Citations
Patent
Vertical memory devices
Chang-Hyun Lee
- 05 Jan 2016
TL;DR: In this paper, a vertical memory device includes a low resistance layer on a lower insulation layer, a channel layer on the low-resistance layer, vertical channels on the channel layer, and a plurality of gate lines.
35
Patent
Three-dimensional memory device containing bonded memory die and peripheral logic die and method of making thereof
Akio Nishida
- 17 Jan 2018
TL;DR: In this paper, a first die includes a three-dimensional memory device and first copper pads, and a second die includes peripheral logic circuitry containing CMOS devices located on the semiconductor substrate and second copper pads.
20
Patent
Three-dimensional memory device containing hydrogen diffusion barrier structures for CMOS under array architecture and method of making the same
Hiroshi Nakatsuji,Kazutaka Yoshizawa,Hiroyuki Ogawa +2 more
- 30 Jun 2017
TL;DR: In this paper, a contact level silicon oxide layer and a silicon nitride layer are formed over a semiconductor device on a silicon substrate, and metal interconnect structures are formed to provide electrical connection between the contact via structure and a node of the 3D memory array.
17
Patent
Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof
Kim Kwang-Ho,Masaaki Higashitani,Fumiaki Toyama,Akio Nishida +3 more
- 09 Jan 2019
TL;DR: In this paper, the logic-side bonding pads are attached to a respective one or a respective subset of the memory side bonding pads, which can be used as a component of a source power distribution network.
15
Patent
Memory devices using etching stop layers
Lee Jeong Gil,Kim Jee Yong,Lee Jung Hwan,Byeon Dae Seok,Lim Hyun Seok +4 more
- 19 Apr 2018
TL;DR: In this paper, a memory device may include a gate structure including a plurality of gate electrode layers, and contacts connected to the gate electrodes above upper portions of the etching stop layers, respectively.
4
References
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TL;DR: In this paper, the etch rates of 53 materials that are used or potentially can be used or in the fabrication of microelectromechanical systems and integrated circuits were prepared.
Patent
Three dimensional structure memory
Glenn J. Leedy
- 17 Mar 2009
TL;DR: The 3Dimensional Structure (3DS) Memory (100) as mentioned in this paper is a three-dimensional structure (3D) memory that allows physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized.
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Etch rates for micromachining processing
TL;DR: The etch rates for 317 combinations of 16 materials (single-crystal silicon, doped, and undoped polysilicon, several types of silicon dioxide, stoichiometric and silicon-rich silicon nitride, aluminum, tungsten, titanium, Ti/W alloy, and two brands of positive photoresist) used in the fabrication of microelectromechanical systems and integrated circuits in 28 wet, plasma, and plasmaless-gas-phase etches (several HF solutions, H/sub 3/PO/sub 4), HNO/sub
•Proceedings Article
Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory
Jae-Hoon Jang,Han-soo Kim,Wonseok Cho,Hoosung Cho,Jinho Kim,Sun Il Shim,Younggoan Jang,Jae-Hun Jeong,Byoungkeun Son,Dongwoo Kim,Kihyun,Jae-Joo Shim,Jin Soo Lim,Kyoung-hoon Kim,Su Youn Yi,Ju-Young Lim,De-will Chung,Hui-chang Moon,Sung-Min Hwang,Jong-Wook Lee,Yong-Hoon Son,U-In Chung,Won-Seong Lee +22 more
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TL;DR: Damascened metal gate SONOS type cell in the vertical NAND flash string is realized by a unique dasiagate replacementpsila process and conventional bulk erase operation of the cell is successfully demonstrated.
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Patent
Non-volatile semiconductor storage device and method of manufacturing the same
Yoshiaki Fukuzumi,Ryota Katsumata,Masaru Kidoh,Masaru Kito,Hiroyasu Tanaka,Yosuke Komori,Megumi Ishiduki,Hideaki Aochi +7 more
- 09 Sep 2009
TL;DR: In this paper, a nonvolatile semiconductor storage device has a plurality of memory strings to each of which an electrically rewritable memory cells are connected in series, each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate.
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