The SPLASH-2 programs

TL;DR: It is demonstrated that a RWHCA design with a conservative setup can provide a geometric mean 55% power reduction and yet 5% IPC improvement over a baseline SRAM cache design across a collection of 30 workloads.

TL;DR: This paper presents an overview of several research efforts that propose to use machine learning techniques for power and thermal management on single-core and multicore processors, and can potentially adapt to varying system conditions and workloads.

TL;DR: This paper proposes A-WiNoC, a scalable, adaptable wireless Network-on-Chip architecture that uses energy efficient wireless transceivers and improves network throughput by dynamically re-assigning channels in response to bandwidth demands from different cores.

TL;DR: It is shown that the integration of wireless interconnects with wired interConnects in NoCs can reduce overall network power by 34 percent while achieving a speedup of 2.54 on real applications.

TL;DR: Standard techniques for shooting and gathering can be used with the hierarchical representation to solve for equilibrium radiosities, but the paper also discusses using a brightness-weighted error criteria, in conjunction with multigridding, to even more rapidly progressively refine the image.

TL;DR: A fast sorting algorithm for the Connection Machine Supercomputer model CM-2 is developed and it is shown that any U(lg n)-depth family of sorting networks can be used to sort n numbers in U( lg n) time in the bounded-degree fixed interconnection network domain.

TL;DR: To mitigate false sharing and to enhance spatial locality, the layout of shared data in cache blocks is optimized in a programmer-transparent manner and it is shown that this approach can reduce the number of misses on shared data by about 10% on average.

TL;DR: Advanced techniques for computing an ordered FFT on a computer with external or hierarchical memory that require as few as two passes through the external data set, employ strictly unit stride, long vector transfers between main memory and external storage, and are well suited for vector and parallel computation are described.